Volume 1 Application Programming (794095), страница 8
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Clarified the general description of theoperation of certain 128-bit media instructions in Chapter 1. Corrected afactual error in the description of the FNINIT/FINIT instructions in Chapter 6.Corrected operand descriptions for the CMOVcc instructions in Chapter 3.Added Revision History. Corrected marketing denotations.September,2002Revision HistoryxvAMD64 Technologyxvi24592—Rev. 3.13—July 2007Revision History24592—Rev. 3.13—July 2007AMD64 TechnologyPrefaceAbout This BookThis book is part of a multivolume work entitled the AMD64 Architecture Programmer’s Manual. Thistable lists each volume and its order number.TitleOrder No.Volume 1: Application Programming24592Volume 2: System Programming24593Volume 3: General-Purpose and System Instructions24594Volume 4: 128-Bit Media Instructions26568Volume 5: 64-Bit Media and x87 Floating-Point Instructions26569AudienceThis volume (Volume 1) is intended for programmers writing application programs, compilers, orassemblers.
It assumes prior experience in microprocessor programming, although it does not assumeprior experience with the legacy x86 or AMD64 microprocessor architecture.This volume describes the AMD64 architecture’s resources and functions that are accessible toapplication software, including memory, registers, instructions, operands, I/O facilities, andapplication-software aspects of control transfers (including interrupts and exceptions) andperformance optimization.System-programming topics—including the use of instructions running at a current privilege level(CPL) of 0 (most-privileged)—are described in Volume 2.
Details about each instruction are describedin volumes 3, 4, and 5.Contact InformationTo submit questions or comments concerning this document, contact our technical documentation staffat AMD64.Feedback@amd.com.OrganizationThis volume begins with an overview of the architecture and its memory organization and is followedby chapters that describe the four application-programming models available in the AMD64architecture:PrefacexviiAMD64 Technology••••24592—Rev. 3.13—July 2007General-Purpose Programming—This model uses the integer general-purpose registers (GPRs).The chapter describing it also describes the basic application environment for exceptions, controltransfers, I/O, and memory optimization that applies to all other application-programming models.128-bit Media Programming—This model uses the 128-bit XMM registers and supports integerand floating-point operations on vector (packed) and scalar data types.64-bit Media Programming—This model uses the 64-bit MMX™ registers and supports integerand floating-point operations on vector (packed) and scalar data types.x87 Floating-Point Programming—This model uses the 80-bit x87 registers and supports floatingpoint operations on scalar data types.Definitions assumed throughout this volume are listed below.
The index at the end of this volumecross-references topics within the volume. For other topics relating to the AMD64 architecture, see thetables of contents and indexes of the other volumes.DefinitionsSome of the following definitions assume a knowledge of the legacy x86 architecture. See “RelatedDocuments” on page xxviii for further information about the legacy x86 architecture.Terms and Notation1011bA binary value—in this example, a 4-bit value.F0EAhA hexadecimal value—in this example a 2-byte value.[1,2)A range that includes the left-most value (in this case, 1) but excludes the right-most value (in thiscase, 2).7–4A bit range, from bit 7 to 4, inclusive. The high-order bit is shown first.128-bit media instructionsInstructions that use the 128-bit XMM registers. These are a combination of the SSE and SSE2instruction sets.64-bit media instructionsInstructions that use the 64-bit MMX registers.
These are primarily a combination of MMX and3DNow!™ instruction sets, with some additional instructions from the SSE and SSE2 instructionsets.xviiiPreface24592—Rev. 3.13—July 2007AMD64 Technology16-bit modeLegacy mode or compatibility mode in which a 16-bit address size is active.
See legacy mode andcompatibility mode.32-bit modeLegacy mode or compatibility mode in which a 32-bit address size is active. See legacy mode andcompatibility mode.64-bit modeA submode of long mode. In 64-bit mode, the default address size is 64 bits and new features, suchas register extensions, are supported for system and application software.#GP(0)Notation indicating a general-protection exception (#GP) with error code of 0.absoluteSaid of a displacement that references the base of a code segment rather than an instruction pointer.Contrast with relative.ASIDAddress space identifier.biased exponentThe sum of a floating-point value’s exponent and a constant bias for a particular floating-point datatype. The bias makes the range of the biased exponent always positive, which allows reciprocationwithout overflow.byteEight bits.clearTo write a bit value of 0. Compare set.compatibility modeA submode of long mode.
In compatibility mode, the default address size is 32 bits, and legacy 16bit and 32-bit applications run without modification.commitTo irreversibly write, in program order, an instruction’s result to software-visible storage, such as aregister (including flags), the data cache, an internal write buffer, or memory.CPLCurrent privilege level.CR0–CR4A register range, from register CR0 through CR4, inclusive, with the low-order register first.PrefacexixAMD64 Technology24592—Rev.
3.13—July 2007CR0.PE = 1Notation indicating that the PE bit of the CR0 register has a value of 1.directReferencing a memory location whose address is included in the instruction’s syntax as animmediate operand. The address may be an absolute or relative address. Compare indirect.dirty dataData held in the processor’s caches or internal buffers that is more recent than the copy held inmain memory.displacementA signed value that is added to the base of a segment (absolute addressing) or an instruction pointer(relative addressing). Same as offset.doublewordTwo words, or four bytes, or 32 bits.double quadwordEight words, or 16 bytes, or 128 bits.
Also called octword.DS:rSIThe contents of a memory location whose segment address is in the DS register and whose offsetrelative to that segment is in the rSI register.EFER.LME = 0Notation indicating that the LME bit of the EFER register has a value of 0.effective address sizeThe address size for the current instruction after accounting for the default address size and anyaddress-size override prefix.effective operand sizeThe operand size for the current instruction after accounting for the default operand size and anyoperand-size override prefix.elementSee vector.exceptionAn abnormal condition that occurs as the result of executing an instruction.
The processor’sresponse to an exception depends on the type of the exception. For all exceptions except 128-bitmedia SIMD floating-point exceptions and x87 floating-point exceptions, control is transferred tothe handler (or service routine) for that exception, as defined by the exception’s vector. Forfloating-point exceptions defined by the IEEE 754 standard, there are both masked and unmaskedxxPreface24592—Rev. 3.13—July 2007AMD64 Technologyresponses. When unmasked, the exception handler is called, and when masked, a default responseis provided instead of calling the handler.FF /0Notation indicating that FF is the first byte of an opcode, and a subopcode in the ModR/M byte hasa value of 0.flushAn often ambiguous term meaning (1) writeback, if modified, and invalidate, as in “flush the cacheline,” or (2) invalidate, as in “flush the pipeline,” or (3) change a value, as in “flush to zero.”GDTGlobal descriptor table.GIFGlobal interrupt flag.IDTInterrupt descriptor table.IGNIgnore.
Field is ignored.indirectReferencing a memory location whose address is in a register or other memory location. Theaddress may be an absolute or relative address. Compare direct.IRBThe virtual-8086 mode interrupt-redirection bitmap.ISTThe long-mode interrupt-stack table.IVTThe real-address mode interrupt-vector table.LDTLocal descriptor table.legacy x86The legacy x86 architecture. See “Related Documents” on page xxviii for descriptions of thelegacy x86 architecture.legacy modeAn operating mode of the AMD64 architecture in which existing 16-bit and 32-bit applications andoperating systems run without modification. A processor implementation of the AMD64PrefacexxiAMD64 Technology24592—Rev.
3.13—July 2007architecture can run in either long mode or legacy mode. Legacy mode has three submodes, realmode, protected mode, and virtual-8086 mode.long modeAn operating mode unique to the AMD64 architecture. A processor implementation of theAMD64 architecture can run in either long mode or legacy mode. Long mode has two submodes,64-bit mode and compatibility mode.lsbLeast-significant bit.LSBLeast-significant byte.main memoryPhysical memory, such as RAM and ROM (but not cache memory) that is installed in a particularcomputer system.mask(1) A control bit that prevents the occurrence of a floating-point exception from invoking anexception-handling routine.
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