Volume 1 Application Programming (794095), страница 40
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The three high-order doublewords in the destination XMMregister are not modified.The CVTSI2SD instruction converts a 32-bit or 64-bit signed integer value in a general-purposeregister or memory location to a double-precision floating-point value and writes the converted valuein the low-order 64 bits of an XMM register.
The high-order 64 bits in the destination XMM registerare not modified.4.5.4 Data ReorderingThe integer data-reordering instructions pack, unpack, interleave, extract, insert, and shuffle theelements of vector operands.Pack with Saturation. These instructions pack larger data types into smaller data types, thus halvingthe precision of each element in a vector operand.•••PACKSSDW—Pack with Saturation Signed Doubleword to WordPACKSSWB—Pack with Saturation Signed Word to BytePACKUSWB—Pack with Saturation Signed Word to Unsigned ByteThe PACKSSDW instruction converts each of the four signed doubleword integers in its two sourceoperands (an XMM register, and another XMM register or 128-bit memory location) into signed wordintegers and packs the converted values into the destination operand (an XMM register).
ThePACKSSWB instruction does the analogous conversion between word elements in the source vectorsand byte elements in the destination vector. The PACKUSWB instruction does the same asPACKSSWB except that it converts signed word integers into unsigned (rather than signed) bytes.140128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007AMD64 TechnologyFigure 4-20 shows an example of a PACKSSDW instruction.
The operation merges vector elements of2x size into vector elements of 1x size, thus reducing the precision of the vector-element data types.Any results that would otherwise overflow or underflow are saturated (clamped) at the maximum orminimum representable value, respectively, as described in “Saturation” on page 125.operand 1operand 21270127127result00513-150.epsFigure 4-20.PACKSSDW Pack OperationConversion from higher-to-lower precision is often needed, for example, by multiplication operationsin which the higher-precision format is used for source operands in order to prevent possible overflow,and the lower-precision format is the desired format for the next operation.Unpack and Interleave. These instructions interleave vector elements from the high or low halves oftwo integer source operands.
They can be used to double the precision of operands.••••••••PUNPCKHBW—Unpack and Interleave High BytesPUNPCKHWD—Unpack and Interleave High WordsPUNPCKHDQ—Unpack and Interleave High DoublewordsPUNPCKHQDQ—Unpack and Interleave High QuadwordsPUNPCKLBW—Unpack and Interleave Low BytesPUNPCKLWD—Unpack and Interleave Low WordsPUNPCKLDQ—Unpack and Interleave Low DoublewordsPUNPCKLQDQ—Unpack and Interleave Low QuadwordsThe PUNPCKHBW instruction copies the eight high-order bytes from its two source operands (anXMM register, and another XMM register or 128-bit memory location) and interleaves them into the128-bit destination operand (an XMM register).
The bytes in the low-order half of the source operandsare ignored. The PUNPCKHWD, PUNPCKHDQ, and PUNPCKHQDQ instructions performanalogous operations for words, doublewords, and quadwords in the source operands, packing them128-Bit Media and Scientific Programming141AMD64 Technology24592—Rev. 3.13—July 2007into interleaved words, interleaved doublewords, and interleaved quadwords in the destinationoperand.The PUNPCKLBW, PUNPCKLWD, PUNPCKLDQ, and PUNPCKLQDQ instructions are analogousto their high-element counterparts except that they take elements from the low quadword of eachsource vector and ignore elements in the high quadword.
Depending on the hardware implementation,if the source operand for PUNPCKLx and PUNPCKHx instructions is in memory, only the low 64 bitsof the operand may be loaded.Figure 4-21 shows an example of the PUNPCKLWD instruction. The elements are taken from the lowhalf of the source operands. In this register image, elements from operand2 are placed to the left ofelements from operand1.operand 1operand 21270.127127..result0.0513-149.epsFigure 4-21. PUNPCKLWD Unpack and Interleave OperationIf operand 2 is a vector consisting of all zero-valued elements, the unpack instructions perform thefunction of expanding vector elements of 1x size into vector elements of 2x size.
Conversion fromlower-to-higher precision is often needed, for example, prior to multiplication operations in which thehigher-precision format is used for source operands in order to prevent possible overflow duringmultiplication.If both source operands are of identical value, the unpack instructions can perform the function ofduplicating adjacent elements in a vector.The PUNPCKx instructions can be used in a repeating sequence to transpose rows and columns of anarray. For example, such a sequence could begin with PUNPCKxWD and be followed byPUNPCKxQD.
These instructions can also be used to convert pixel representation from RGB formatto color-plane format, or to interleave interpolation elements into a vector.As noted above, and depending on the hardware implementation, the width of the memory accessperformed by the memory-operand forms of PUNPCKLBW, PUNPCKLWD, PUNPCKLDQ, and142128-Bit Media and Scientific Programming24592—Rev.
3.13—July 2007AMD64 TechnologyPUNPCKLQDQ may be 64 bits, but the width of the memory access of the memory-operand forms ofPUNPCKHBW, PUNPCKHWD, PUNPCKHDQ, and PUNPCKHQDQ may be 128 bits. Thus, thealignment constraints for PUNPCKLx instructions may be less restrictive than the alignmentconstraints for PUNPCKHx instructions.
For details, see the documentation for particular hardwareimplementations of the architecture.Another advantage of using PUNPCKLx rather than PUNPCKHx—also depending on the hardwareimplementation—is that it may help avoid potential size mismatches if a particular hardwareimplementation uses load-to-store forwarding. In such cases, store data from either a quadword storeor the lower quadword of a double-quadword store could be forwarded to PUNPCKLx instructions,but only store data from a double-quadword store could be forwarded to PUNPCKHx instructions.The PUNPCKx instructions—along with the MOVx instructions—are often among the mostfrequently used instructions in 128-bit media integer and floating-point procedures.Extract and Insert.
These instructions copy a word element from a vector, in a manner specified byan immediate operand.••••EXTRQ—Extract Field from RegisterINSERTQ—Insert FieldPEXTRW—Packed Extract WordPINSRW—Packed Insert WordThe EXTRQ instruction extracts specified bits from the lower 64 bits of the destination XMM register.The extracted bits are saved in the least-significant bit positions of the destination and the remainingbits in the lower 64 bits of the destination register are cleared to 0. The upper 64 bits of the destinationregister are undefined.The INSERTQ instruction inserts a specified number of bits from the lower 64 bits of the sourceoperand into a specified bit position of the lower 64 bits of the destination operand.
No other bits in thelower 64 bits of the destination are modified. The upper 64 bits of the destination are undefined.The PEXTRW instruction extracts a 16-bit value from an XMM register, as selected by the immediatebyte operand, and writes it to the low-order word of a 32-bit or 64-bit general-purpose register, withzero-extension to 32 or 64 bits.
PEXTRW is useful for loading computed values, such as table-lookupindices, into general-purpose registers where the values can be used for addressing tables in memory.The PINSRW instruction inserts a 16-bit value from the low-order word of a general-purpose registeror from a 16-bit memory location into an XMM register. The location in the destination register isselected by the immediate-byte operand. The other words in the destination register operand are notmodified. Figure 4-22 on page 144 shows the operation.128-Bit Media and Scientific Programming143AMD64 Technology24592—Rev. 3.13—July 2007xmmreg32/64/mem161270150imm8select word position for insert1270result513-166.epsFigure 4-22.
PINSRW OperationShuffle. These instructions reorder the elements of a vector.•••PSHUFD—Packed Shuffle DoublewordsPSHUFHW—Packed Shuffle High WordsPSHUFLW—Packed Shuffle Low WordsThe PSHUFD instruction fills each doubleword of the first operand (an XMM register) by copying anyone of the doublewords in the second operand (an XMM register or 128-bit memory location).
Theordering of the shuffle can occur in one of 256 possible ways, as specified by the third operand, animmediate byte. Figure 4-23 on page 145 shows one of the 256 possible shuffle operations.144128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007AMD64 Technologyoperand 1operand 2127012712700result513-151.epsFigure 4-23.PSHUFD Shuffle OperationThe PSHUFHW and PSHUFLW instructions are analogous to PSHUFD, except that they fill eachword of the high or low quadword, respectively, of the first operand by copying any one of the fourwords in the high or low quadword of the second operand.
Figure 4-24 shows the PSHUFHWoperation. PSHUFHW and PSHUFLW are useful, for example, in color imaging when computingalpha saturation of RGB values. In this case, PSHUFxW can replicate an alpha value in a register sothat parallel comparisons with three RGB values can be performed.operand 1127operand 20127127result00513-167.epsFigure 4-24. PSHUFHW Shuffle Operation4.5.5 ArithmeticThe integer vector-arithmetic instructions perform an arithmetic operation on the elements of twosource vectors. Figure 4-25 on page 146 shows a typical arithmetic operation on vectors of bytes.
Suchinstructions performs 16 arithmetic operations in parallel.128-Bit Media and Scientific Programming145AMD64 Technology24592—Rev. 3.13—July 2007operand 1operand 21270127. . . . . . . . . . . . . .0. . . . . . . . . . . . . .operationoperation. . . . . . .
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