Volume 1 Application Programming (794095), страница 38
Текст из файла (страница 38)
The NaN result is produced when the floating-point invalid-operation exception is masked.2. The conversion is done by changing the most-significant fraction bit to 1.3. See “Indefinite Values” on page 131.4.4.8 Floating-Point Number EncodingsSupported Encodings.
Table 4-6 on page 131 shows the floating-point encodings of supportednumbers and non-numbers. The number categories are ordered from large to small. In this affineordering, positive infinity is larger than any positive normalized number, which in turn is larger thanany positive denormalized number, which is larger than positive zero, and so forth.
Thus, the ordinaryrules of comparison apply between categories as well as within categories, so that comparison of anytwo numbers is well-defined.The actual exponent field length is 8 or 11 bits, and the fraction field length is 23 or 52 bits, dependingon operand precision. The single-precision and double-precision formats do not include the integer bitin the significand (the value of the integer bit can be inferred from number encodings). Exponents ofboth types are encoded in biased format, with respective biasing constants of 127 and 1023.130128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007Table 4-6.AMD64 TechnologySupported Floating-Point EncodingsClassificationSignNegativeFloating-PointNumbersSignificand2SNaN01.011 ...
111111 ... 111 to1.000 ... 001QNaN01.111 ... 111111 ... 111 to1.100 ... 000Positive Infinity (+∞)0111 ... 111 1.000 ... 000Positive Normal0111 ... 110 1.111 ... 111toto000 ... 001 1.000 ... 000Positive Denormal00.111 ... 111000 ... 000 to0.000 ... 001Positive Zero0000 ... 000 0.000 ... 000Negative Zero1000 ... 000 0.000 ... 000Negative Denormal10.000 ... 001000 ... 000 to0.111 ...
1111000 ... 001 1.000 ... 000toto111 ... 110 1.111 ... 111Negative Infinity (–∞) 1111 ... 111 1.000 ... 000SNaN11.000 ... 001111 ... 111 to1.011 ... 11111.100 ... 000111 ... 111 to1.111 ... 111PositiveNon-NumbersPositiveFloating-PointNumbersBiasedExponent1Negative NormalNegativeNon-NumbersQNaN3Note:1.
The actual exponent field length is 8 or 11 bits, depending on operand precision.2. The “1.” and “0.” prefixes represent the implicit integer bit. The actual fraction fieldlength is 23 or 52 bits, depending on operand precision.3. The floating-point indefinite value is a QNaN with a negative sign and a significandwhose value is 1.100 ... 000.Indefinite Values. Floating-point and integer data type each have a unique encoding that representsan indefinite value. The processor returns an indefinite value when a masked invalid-operationexception (IE) occurs.For example, if a floating-point division operation is attempted using source operands that are bothzero, and IE exceptions are masked, the floating-point indefinite value is returned as the result. Or, if a128-Bit Media and Scientific Programming131AMD64 Technology24592—Rev.
3.13—July 2007floating-point-to-integer data conversion overflows its destination integer data type, and IE exceptionsare masked, the integer indefinite value is returned as the result.Table 4-7 shows the encodings of the indefinite values for each data type. For floating-point numbers,the indefinite value is a special form of QNaN. For integers, the indefinite value is the largestrepresentable negative twos-complement number, 80...00h. (This value is the largest representablenegative number, except when a masked IE exception occurs, in which case it is generated as theindefinite value.)Table 4-7. Indefinite-Value EncodingsData TypeIndefinite EncodingSingle-Precision Floating-PointFFC0_0000hDouble-Precision Floating-PointFFF8_0000_0000_0000h16-Bit Integer8000h32-Bit Integer8000_0000h64-Bit Integer8000_0000_0000_0000h4.4.9 Floating-Point RoundingBits 14–13 of the MXCSR control and status register (“MXCSR Register” on page 117) comprise thefloating-point rounding control (RC) field, which specifies how the results of floating-pointcomputations are rounded.
Rounding modes apply to most arithmetic operations. When roundingoccurs, the processor generates a precision exception (PE). Rounding is not applied to operations thatproduce NaN results.The IEEE 754 standard defines the four rounding modes as shown in Table 4-8.Table 4-8.RC ValueTypes of RoundingModeType of RoundingRound to nearestThe rounded result is the representable value closest to the infinitelyprecise result. If equally close, the even value (with least-significant bit 0)is taken.01Round downThe rounded result is closest to, but no greater than, the infinitely preciseresult.10Round upThe rounded result is closest to, but no less than, the infinitely preciseresult.11Round toward zeroThe rounded result is closest to, but no greater in absolute value than, theinfinitely precise result.00(default)Round to nearest is the default rounding mode.
It provides a statistically unbiased estimate of the trueresult, and is suitable for most applications. The other rounding modes are directed roundings: roundup (toward +∞), round down (toward –∞), and round toward zero. Round up and round down are used132128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007AMD64 Technologyin interval arithmetic, in which upper and lower bounds bracket the true result of a computation.Round toward zero takes the smaller in magnitude, that is, always truncates.The processor produces a floating-point result defined by the IEEE standard to be infinitely precise.This result may not be representable exactly in the destination format, because only a subset of thecontinuum of real numbers finds exact representation in any particular floating-point format.Rounding modifies such a result to conform to the destination format, thereby making the resultinexact and also generating a precision exception (PE), as described in “SIMD Floating-PointException Causes” on page 178.Suppose, for example, the following 24-bit result is to be represented in single-precision format, where“E2 1010” represents the biased exponent:1.0011 0101 0000 0001 0010 0111 E2 1010This result has no exact representation, because the least-significant 1 does not fit into the singleprecision format, which allows for only 23 bits of fraction.
The rounding control field determines thedirection of rounding. Rounding introduces an error in a result that is less than one unit in the last place(ulp), that is, the least-significant bit position of the floating-point representation.4.5Instruction Summary—Integer InstructionsThis section summarizes functions of the integer instructions in the 128-bit media instruction subset.These include integer instructions that use an XMM register for source or destination and dataconversion instructions that convert from integers to floating-point formats. For a summary of thefloating-point instructions in the 128-bit media instruction subset, including data-conversioninstructions that convert from floating-point to integer formats, see “Instruction Summary—FloatingPoint Instructions” on page 156.The instructions are organized here by functional group—such as data-transfer, vector arithmetic, andso on.
Software running at any privilege level can use any of these instructions, if the CPUIDinstruction reports support for the instructions (see “Feature Detection” on page 176). More detail onindividual instructions is given in the alphabetically organized “128-Bit Media Instruction Reference”in Volume 4.4.5.1 SyntaxEach instruction has a mnemonic syntax used by assemblers to specify the operation and the operandsto be used for source and destination (result) data. The majority of 128-bit media integer instructionshave the following syntax:MNEMONIC xmm1, xmm2/mem128Figure 4-16 on page 134 shows an example of the mnemonic syntax for a packed add bytes (PADDB)instruction.128-Bit Media and Scientific Programming133AMD64 Technology24592—Rev. 3.13—July 2007PADDB xmm1, xmm2/mem128MnemonicFirst Source Operandand Destination OperandSecond Source OperandFigure 4-16.513-147.epsMnemonic Syntax for Typical InstructionThis example shows the PADDB mnemonic followed by two operands, a 128-bit XMM registeroperand and another 128-bit XMM register or 128-bit memory operand.
In most instructions that taketwo operands, the first (left-most) operand is both a source operand and the destination operand. Thesecond (right-most) operand serves only as a source. Some instructions can have one or more prefixesthat modify default properties, as described in “Instruction Prefixes” on page 175.Mnemonics. The following characters are used as prefixes in the mnemonics of integer instructions:••••••CVT—ConvertCVTT—Convert with truncationP—Packed (vector)PACK—Pack elements of 2x data size to 1x data sizePUNPCK—Unpack and interleave elementsUNPCK—Unpack and interleave elementsIn addition to the above prefix characters, the following characters are used elsewhere in themnemonics of integer instructions:••••••••••B—ByteD—DoublewordDQ—Double quadwordH—HighL—Low, or LeftPD—Packed double-precision floating-pointPI—Packed integerPS—Packed single-precision floating-pointQ—QuadwordR—Right134128-Bit Media and Scientific Programming24592—Rev.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
