Volume 1 Application Programming (794095), страница 35
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Operation ofthe 128-bit media instructions is supported by the MXCSR control and status register. A few 128-bitmedia instructions—those that perform data conversion or move operations—can have operandslocated in MMX™ registers or general-purpose registers (GPRs).4.3.1 XMM RegistersSixteen 128-bit XMM data registers, xmm0–xmm15, support the 128-bit media instructions.Figure 4-12 on page 117 shows these registers. They can hold operands for both vector and scalaroperations with integer and floating-point data types. The high eight XMM registers, xmm8–xmm15,are available to software running in 64-bit mode for instructions that use a REX prefix (see “REXPrefixes” on page 74).116128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007AMD64 TechnologyXMM Data Registers1270xmm0xmm1xmm2xmm3xmm4xmm5xmm6xmm7xmm8xmm9xmm10xmm11xmm12xmm13xmm14xmm15Available in all modesAvailable only in 64-bit mode128-Bit Media Control and Status RegisterMXCSR310513-314.epsFigure 4-12.128-Bit Media RegistersUpon power-on reset, all 16 XMM registers are cleared to +0.0.
However, initialization by means ofthe #INIT external input signal does not change the state of the XMM registers.4.3.2 MXCSR RegisterFigure 4-13 on page 118 shows a detailed view of the 128-bit media-instruction control and statusregister (MXCSR). All bits in this register are read/write. The fields within the MXCSR apply only tooperations performed by 128-bit media instructions. Software can load the register from memory128-Bit Media and Scientific Programming117AMD64 Technology24592—Rev.
3.13—July 2007using the FXRSTOR or LDMXCSR instructions, and it can store the register to memory using theFXSAVE or STMXCSR instructions.31Reserved, MBZBits31–1817161514–13Mnemonic–MM–FZRC1211109876PMUMOMZMDMIMDAZ543210PEUEOEZEDEIE18 17 16 15 14 13 12 11 10 9 8 7RMFRP U O Z D IeMZCM M M M M MsDescriptionReserved, MBZMisaligned Exception MaskReserved, MBZFlush-to-Zero for Masked UnderflowFloating-Point Rounding ControlException MasksPrecision Exception MaskUnderflow Exception MaskOverflow Exception MaskZero-Divide Exception MaskDenormalized-Operand Exception MaskInvalid-Operation Exception MaskDenormals Are ZerosException FlagsPrecision ExceptionUnderflow ExceptionOverflow ExceptionZero-Divide ExceptionDenormalized-Operand ExceptionInvalid-Operation ExceptionFigure 4-13.6 5 4 3 2 1 0DP U O Z D IAE E E E E EZReset Bit-Value00001111110000000128-Bit Media Control and Status Register (MXCSR)On power-on reset, all bits are initialized to the values provided in Figure 4-13.
However, initializationby means of the #INIT external input signal does not change the state of the XMM registers.The six exception flags (IE, DE, ZE, OE, UE, PE) are sticky bits. (Once set by the processor, such a bitremains set until software clears it.) For details about the causes of SIMD floating-point exceptionsindicated by bits 5–0, see “SIMD Floating-Point Exception Causes” on page 178.
For details about themasking of these exceptions, see “SIMD Floating-Point Exception Masking” on page 184.Invalid-Operation Exception (IE). Bit 0. The processor sets this bit to 1 when an invalid-operationexception occurs. These exceptions are caused by many types of errors, such as an invalid operand.Denormalized-Operand Exception (DE). Bit 1. The processor sets this bit to 1 when one of thesource operands of an instruction is in denormalized form, except that if software has set the118128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007AMD64 Technologydenormals are zeros (DAZ) bit, the processor does not set the DE bit. (See “Denormalized (Tiny)Numbers” on page 128.)Zero-Divide Exception (ZE).
Bit 2. The processor sets this bit to 1 when a non-zero number isdivided by zero.Overflow Exception (OE). Bit 3. The processor sets this bit to 1 when the absolute value of arounded result is larger than the largest representable normalized floating-point number for thedestination format. (See “Normalized Numbers” on page 128.)Underflow Exception (UE).
Bit 4. The processor sets this bit to 1 when the absolute value of arounded non-zero result is too small to be represented as a normalized floating-point number for thedestination format. (See “Normalized Numbers” on page 128.)When masked by the UM bit (bit 11), the processor only reports a UE exception if the UE occurstogether with a precision exception (PE).
Also, see bit 15, the flush-to-zero (FZ) bit.Precision Exception (PE). Bit 5. The processor sets this bit to 1 when a floating-point result, afterrounding, differs from the infinitely precise result and thus cannot be represented exactly in thespecified destination format. The PE exception is also called the inexact-result exception.Denormals Are Zeros (DAZ). Bit 6.
Software can set this bit to 1 to enable the DAZ mode, if thehardware implementation supports this mode. In the DAZ mode, when the processor encounterssource operands in the denormalized format it converts them to signed zero values, with the sign of thedenormalized source operand, before operating on them, and the processor does not set thedenormalized-operand exception (DE) bit, regardless of whether such exceptions are masked orunmasked.Support for the DAZ bit is indicated by the MXCSR Mask field in the FXSAVE memory image, asdescribed in “FXSAVE and FXRSTOR Instructions” in Volume 2.
The DAZ mode does not complywith the IEEE Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Std 754).Exception Masks (PM, UM, OM, ZM, DM, IM). Bits 12–7. Software can set these bits to mask, orclear this bits to unmask, the corresponding six types of SIMD floating-point exceptions (PE, UE, OE,ZE, DE, IE). A bit masks its exception type when set to 1, and unmasks it when cleared to 0.In general, masking a type of exception causes the processor to handle all subsequent instances of theexception type in a default way (the UE exception has an unusual behavior). Unmasking the exceptiontype causes the processor to branch to the SIMD floating-point exception service routine when anexception occurs. For details about the processor’s responses to masked and unmasked exceptions, see“SIMD Floating-Point Exception Masking” on page 184.Floating-Point Rounding Control (RC).
Bit 14–13. Software uses these bits to specify the roundingmethod for 128-bit media floating-point operations. The choices are:••00 = round to nearest (default)01 = round down128-Bit Media and Scientific Programming119AMD64 Technology••24592—Rev. 3.13—July 200710 = round up11 = round toward zeroFor details, see “Floating-Point Rounding” on page 132.Flush-to-Zero (FZ). Bit 15. If the rounded result is tiny and the underflow mask is set, the FTZ bitcauses the result to be flushed to zero. This naturally causes the result to be inexact, which causes bothPE and UE to be set. The sign returned with the zero is the sign of the true result. The FTZ bit does nothave any effect if the underflow mask is 0.This response does not comply with the IEEE 754 standard, but it may offer higher performance thancan be achieved by responding to an underflow in this circumstance.
The FZ bit is only effective if theUM bit is set to 1. If the UM bit is cleared to 0, the FZ bit is ignored. For details, see Table 4-14 onpage 185.Misaligned Exception Mask (MM). Bit 17. If the misaligned exception mask (MM) is set to 1, a 16-byte misaligned memory access on most packed SSE instructions will not cause a #GP exception, butwill be subject to alignment checking (#AC) instead. When MM is set and alignment-checking isenabled, a #AC exception is generated, if the memory operand is not 16-byte aligned. Thecorresponding MXCSR_MASK bit (17) is 1, regardless of whether MM is set or not.
For details onMXCSR and MXCSR_MASK, see “128-Bit, 64-Bit, and x87 Programming” in the AMD64Architecture Programmer’s Manual Volume 2: System Programming, order #24593.Support for misaligned SSE mode is indicated by ECX bit 7 of CPUID function 8000_0001h.4.3.3 Other Data RegistersSome 128-bit media instructions that perform data transfer, data conversion or data reorderingoperations (“Data Transfer” on page 135, “Data Conversion” on page 139, and “Data Reordering” onpage 140) can access operands in the MMX or general-purpose registers (GPRs).
When addressingGPRs registers in 64-bit mode, the REX instruction prefix can be used to access the extended GPRs, asdescribed in “REX Prefixes” on page 74.For a description of the GPR registers, see “Registers” on page 23. For a description of the MMXregisters, see “MMX™ Registers” on page 200.4.3.4 rFLAGS RegistersThe COMISS, COMISD, UCOMISS, and UCOMISD instructions, described in “Compare” onpage 171, write flag bits in the rFLAGS register. For a description of the rFLAGS register, see “FlagsRegister” on page 33.4.4OperandsOperands for a 128-bit media instruction are either referenced by the instruction's opcode or includedas an immediate value in the instruction encoding. Depending on the instruction, referenced operands120128-Bit Media and Scientific Programming24592—Rev.
3.13—July 2007AMD64 Technologycan be located in registers or memory. The data types of these operands include vector and scalarfloating-point, and vector and scalar integer.4.4.1 Data TypesFigure 4-14 on page 122 shows the register images of the 128-bit media data types. These data typescan be interpreted by instruction syntax and/or the software context as one of the following types ofvalues:••••••Vector (packed) single-precision (32-bit) floating-point numbers.Vector (packed) double-precision (64-bit) floating-point numbers.Vector (packed) signed (two's-complement) integers.Vector (packed) unsigned integers.Scalar signed (two's-complement) integers.Scalar unsigned integers.Hardware does not check or enforce the data types for instructions.
Software is responsible forensuring that each operand for an instruction is of the correct data type. If data produced by a previousinstruction is of a type different from that used by the current instruction, and the current instructionsources such data, the current instruction may incur a latency penalty, depending on the hardwareimplementation.128-Bit Media and Scientific Programming121AMD64 Technology24592—Rev. 3.13—July 2007Vector (Packed) Floating-Point Double Precision and Single Precision127115ssexpssexp63significandsignificand127ss118exp95significand8651ssexpssexp630significandsignificandss54exp31significand220Vector (Packed) Signed Integer Quadword, Doubleword, Word, Bytequadwordssdoublewordsswordssssbyte127bytess119bytess111doublewordsswordssbytesswordss103ssquadwordssbyte95ssbyte87wordssssbyte79doublewordssssbyte71sssswordbytess63byte55sssswordbyte47doublewordsssswordssbyte39ssbyte31ssssbyte23sswordbyte15ssbyte70Vector (Packed) Unsigned Integer Quadword, Doubleword, Word, Bytequadwordquadworddoublewordwordbyte127byte119doublewordwordbyte111wordbyte103byte95wordbyte87doublewordbyte79wordbyte71bytewordbyte6355doublewordbyte47wordbyte39byte31wordbyte23byte15byte70Scalar Floating-Point Double Precision and Single Precisionssexp63significand51sssignificandexp31220Scalar Unsigned Integersdouble quadword1271270quadworddoubleword6331word15byte7Figure 4-14.122bit0513-316.eps128-Bit Media Data Types128-Bit Media and Scientific Programming24592—Rev.
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