Volume 1 Application Programming (794095), страница 31
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Internal caches contain copies of the mostfrequently-used instructions and data found in main memory and external caches, and theircapacities are relatively small in comparison to external caches. A processor implementation cancontain any number of internal caches, or none at all. Implementations often contain a first-levelinstruction cache and first-level data (operand) cache, and they may also contain a higher-capacity(and slower) second-level internal cache for storing both instructions and data.Figure 3-19 on page 97 shows an example of a four-level memory hierarchy that combines mainmemory, external third-level (L3) cache, and internal second-level (L2) and two first-level (L1) caches.As the figure shows, the first-level and second-level caches are implemented on the processor chip, andthe third-level cache is external to the processor.
The first-level cache is a split cache, with separatecaches used for instructions and data. The second-level and third-level caches are unified (they containboth instructions and data). Memory at the highest levels of the hierarchy have greater capacity (largersize), but have slower access, than memory at the lowest levels.Using caches to store frequently used instructions and data can result in significantly improvedsoftware performance by avoiding accesses to the slower main memory. Applications functionidentically on systems without caches and on systems with caches, although cacheless systemstypically execute applications more slowly. Application software can, however, be optimized to makeefficient use of caches when they are present, as described later in this section.96General-Purpose Programming24592—Rev. 3.13—July 2007AMD64 TechnologyLargerSizeMain MemoryL3 CacheSystemL2 CacheFasterAccessL1 InstructionCacheL1 DataCacheProcessor513-137.epsFigure 3-19.
Memory Hierarchy ExampleWrite Buffering. Processor implementations can contain write-buffers attached to the internalcaches. Write buffers can also be present on the interface used to communicate with the externalportions of the memory hierarchy. Write buffers temporarily hold data writes when main memory orthe caches are busy responding to other memory-system accesses. The existence of write buffers istransparent to software. However, some of the instructions used to optimize memory-hierarchyperformance can affect the write buffers, as described in “Forcing Memory Order” on page 94.3.9.4 Cache OperationAlthough the existence of caches is transparent to application software, a simple understanding howcaches are accessed can assist application developers in optimizing their code to run efficiently whencaches are present.Caches are divided into fixed-size blocks, called cache lines. Typically, implementations have either32-byte or 64-byte cache lines.
The processor allocates a cache line to correspond to an identicallysized region in main memory. After a cache line is allocated, the addresses in the corresponding regionof main memory are used as addresses into the cache line. It is the processor’s responsibility to keepthe contents of the allocated cache line coherent with main memory.
Should another system deviceGeneral-Purpose Programming97AMD64 Technology24592—Rev. 3.13—July 2007access a memory address that is cached, the processor maintains coherency by providing the correctdata back to the device and main memory.When a memory-read occurs as a result of an instruction fetch or operand access, the processor firstchecks the cache to see if the requested information is available. A read hit occurs if the information isavailable in the cache, and a read miss occurs if the information is not available. Likewise, a write hitoccurs if a memory write can be stored in the cache, and a write miss occurs if it cannot be stored in thecache.A read miss or write miss can result in the allocation of a cache line, followed by a cache-line fill. Evenif only a single byte is needed, all bytes in a cache line are loaded from memory by a cache-line fill.Typically, a cache-line fill must write over an existing cache line in a process called a cache-linereplacement.
In this case, if the existing cache line is modified, the processor performs a cache-linewriteback to main memory prior to performing the cache-line fill.Cache-line writebacks help maintain coherency between the caches and main memory. Internally, theprocessor can also maintain cache coherency by internally probing (checking) the other caches andwrite buffers for a more recent version of the requested data. External devices can also check aprocessor’s caches and write buffers for more recent versions of data by externally probing theprocessor. All coherency operations are performed in hardware and are completely transparent toapplications.Cache Coherency and MOESI.
Implementations of the AMD64 architecture maintain coherencybetween memory and caches using a five-state protocol known as MOESI. The five MOESI states aremodified, owned, exclusive, shared, and invalid. See “Memory System” in Volume 2 for additionalinformation on MOESI and cache coherency.Self-Modifying Code. Software that writes into a code segment is classified as self-modifying code.To avoid cache-coherency problems due to self-modifying code, implementations of the AMD64architecture invalidate an instruction cache line during a memory write if the instruction cache linecorresponds to a code-segment memory location. By invalidating the instruction cache line, theprocessor is forced to write the modified instruction into main memory.
A subsequent fetch of themodified instruction goes to main memory to get the coherent version of the instruction.3.9.5 Cache PollutionBecause cache sizes are limited, caches should be filled only with data that is frequently used by anapplication. Data that is used infrequently, or not at all, is said to pollute the cache because it occupiesotherwise useful cache lines. Ideally, the best data to cache is data that adheres to the principle oflocality. This principle has two components: temporal locality and spatial locality.•98Temporal locality refers to data that is likely to be used more than once in a short period of time.
Itis useful to cache temporal data because subsequent accesses can retrieve the data quickly. Nontemporal data is assumed to be used once, and then not used again for a long period of time, or ever.Caching of non-temporal data pollutes the cache and should be avoided.General-Purpose Programming24592—Rev. 3.13—July 2007•AMD64 TechnologyCache-control instructions (“Cache-Control Instructions” on page 99) are available to applicationsto minimize cache pollution caused by non-temporal data.Spatial locality refers to data that resides at addresses adjacent to or very close to the data beingreferenced. Typically, when data is accessed, it is likely the data at nearby addresses will beaccessed in a short period of time.
Caches perform cache-line fills in order to take advantage ofspatial locality. During a cache-line fill, the referenced data and nearest neighbors are loaded intothe cache. If the characteristics of spacial locality do not fit the data used by an application, then thecache becomes polluted with a large amount of unreferenced data.Applications can avoid problems with this type of cache pollution by using data structures withgood spatial-locality characteristics.Another form of cache pollution is stale data.
Data that adheres to the principle of locality can becomestale when it is no longer used by the program, or won’t be used again for a long time. Applications canuse the CLFLUSH instruction to remove stale data from the cache.3.9.6 Cache-Control InstructionsGeneral control and management of the caches is performed by system software and not applicationsoftware. System software uses special registers to assign memory types to physical-address ranges,and page-attribute tables are used to assign memory types to virtual address ranges. Memory typesdefine the cacheability characteristics of memory regions and how coherency is maintained with mainmemory.
See “Memory System” in Volume 2 for additional information on memory typing.Instructions are available that allow application software to control the cacheability of data it uses on amore limited basis. These instructions can be used to boost an application’s performance byprefetching data into the cache, and by avoiding cache pollution. Run-time analysis tools andcompilers may be able to suggest the use of cache-control instructions for critical sections ofapplication code.Cache Prefetching. Applications can prefetch entire cache lines into the caching hierarchy using oneof the prefetch instructions. The prefetch should be performed in advance, so that the data is availablein the cache when needed.
Although load instructions can mimic the prefetch function, they do notoffer the same performance advantage, because a load instruction may cause a subsequent instructionto stall until the load completes, but a prefetch instruction will never cause such a stall. Loadinstructions also unnecessarily require the use of a register, but prefetch instructions do not.The instructions available in the AMD64 architecture for cache-line prefetching include one SSEinstruction and two 3DNow! instructions:•PREFETCHlevel—(an SSE instruction) Prefetches read/write data into a specific level of thecache hierarchy. If the requested data is already in the desired cache level or closer to the processor(lower cache-hierarchy level), the data is not prefetched.
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