Volume 1 Application Programming (794095), страница 42
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Therounded average is computed by adding each pair of operands, adding 1 to the temporary sum, andthen right-shifting the temporary sum by one bit-position. For vectors of n number of elements, theoperation is:150128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007AMD64 Technologyoperand1[i] = ((operand1[i] + operand2[i]) + 1)÷ 2where: i = 0 to n – 1The PAVGB instruction is useful for MPEG decoding, in which motion compensation performs manybyte-averaging operations between and within macroblocks. In addition to speeding up theseoperations, PAVGB can free up registers and make it possible to unroll the averaging loops.Sum of Absolute Differences.•PSADBW—Packed Sum of Absolute Differences of Bytes into a WordThe PSADBW instruction computes the absolute values of the differences of corresponding 8-bitsigned integer values in the two quadword halves of both source operands, sums the differences foreach quadword half, and writes the two unsigned 16-bit integer results in the destination.
The sum forthe high-order half is written in the least-significant word of the destination’s high-order quadword,with the remaining bytes cleared to all 0s. The sum for the low-order half is written in the leastsignificant word of the destination’s low-order quadword, with the remaining bytes cleared to all 0s.Figure 4-29 shows the PSADBW operation.
Sums of absolute differences are useful, for example, incomputing the L1 norm in motion-estimation algorithms for video compression.operand 1operand 21270. . . . . .ABS Δ127. . . . . .high-orderintermediate result......0. . . . . .ABS ΔABS ΔΣ0127. . . . . .low-orderintermediate result......ABS ΔΣ0result0513-155.epsFigure 4-29. PSADBW Sum-of-Absolute-Differences Operation128-Bit Media and Scientific Programming151AMD64 Technology24592—Rev. 3.13—July 20074.5.6 ShiftThe vector-shift instructions are useful for scaling vector elements to higher or lower precision,packing and unpacking vector elements, and multiplying and dividing vector elements by powers of 2.Left Logical Shift.••••PSLLW—Packed Shift Left Logical WordsPSLLD—Packed Shift Left Logical DoublewordsPSLLQ—Packed Shift Left Logical QuadwordsPSLLDQ—Packed Shift Left Logical Double QuadwordThe PSLLW, PSLLD, and PSLLQ instructions left-shift each of the 16-bit, 32-bit, or 64-bit values,respectively, in the first operand by the number of bits specified in the second operand.
Theinstructions then write each shifted value into the corresponding, same-sized element of thedestination. The low-order bits that are emptied by the shift operation are cleared to 0. The firstoperand is an XMM register. The second operand can be an XMM register, 128-bit memory location,or immediate byte.In integer arithmetic, left logical shifts effectively multiply unsigned operands by positive powers of 2.Thus, for vectors of n number of elements, the operation is:operand1[i] = operand1[i] * 2operand2where: i = 0 to n – 1The PSLLDQ instruction differs from the other three left-shift instructions because it operates on bytesrather than bits. It left-shifts the 128-bit (double quadword) value in an XMM register by the numberof bytes specified in an immediate byte value.Right Logical Shift.••••PSRLW—Packed Shift Right Logical WordsPSRLD—Packed Shift Right Logical DoublewordsPSRLQ—Packed Shift Right Logical QuadwordsPSRLDQ—Packed Shift Right Logical Double QuadwordThe PSRLW, PSRLD, and PSRLQ instructions right-shift each of the 16-bit, 32-bit, or 64-bit values,respectively, in the first operand by the number of bits specified in the second operand.
Theinstructions then write each shifted value into the corresponding, same-sized element of thedestination. The high-order bits that are emptied by the shift operation are cleared to 0. The firstoperand is an XMM register. The second operand can be an XMM register, 128-bit memory location,or immediate byte.In integer arithmetic, right logical bit-shifts effectively divide unsigned operands by positive powers of2, or they divide positive signed operands by positive powers of 2. Thus, for vectors of n number ofelements, the operation is:152128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007operand1[i] = operand1[i]AMD64 Technology÷ 2operand2where: i = 0 to n – 1The PSRLDQ instruction differs from the other three right-shift instructions because it operates onbytes rather than bits.
It right-shifts the 128-bit (double quadword) value in an XMM register by thenumber of bytes specified in an immediate byte value. PSRLDQ can be used, for example, to move thehigh 8 bytes of an XMM register to the low 8 bytes of the register. In some implementations, however,PUNPCKHQDQ may be a better choice for this operation.Right Arithmetic Shift.••PSRAW—Packed Shift Right Arithmetic WordsPSRAD—Packed Shift Right Arithmetic DoublewordsThe PSRAx instructions right-shift each of the 16-bit (PSRAW) or 32-bit (PSRAD) values in the firstoperand by the number of bits specified in the second operand. The instructions then write each shiftedvalue into the corresponding, same-sized element of the destination.
The high-order bits that areemptied by the shift operation are filled with the sign bit of the initial value.In integer arithmetic, right arithmetic shifts effectively divide signed operands by positive powers of 2.Thus, for vectors of n number of elements, the operation is:operand1[i] = operand1[i] ÷ 2operand2where: i = 0 to n – 14.5.7 CompareThe integer vector-compare instructions compare two operands, and they either write a mask or theywrite the maximum or minimum value.Compare and Write Mask.••••••PCMPEQB—Packed Compare Equal BytesPCMPEQW—Packed Compare Equal WordsPCMPEQD—Packed Compare Equal DoublewordsPCMPGTB—Packed Compare Greater Than Signed BytesPCMPGTW—Packed Compare Greater Than Signed WordsPCMPGTD—Packed Compare Greater Than Signed DoublewordsThe PCMPEQx and PCMPGTx instructions compare corresponding bytes, words, or doublewords inthe two source operands.
The instructions then write a mask of all 1s or 0s for each compare into thecorresponding, same-sized element of the destination. Figure 4-30 on page 154 shows a PCMPEQBcompare operation. It performs 16 compares in parallel.128-Bit Media and Scientific Programming153AMD64 Technology24592—Rev. 3.13—July 2007operand 1operand 21270. . . . . . . . . .
. . . .127imm80. . . . . . . . . . . . . .comparecompareall 1s or 0sall 1s or 0s. . . . . . . . . . . . . .127Figure 4-30.result0513-168.epsPCMPEQB Compare OperationFor the PCMPEQx instructions, if the compared values are equal, the result mask is all 1s. If the valuesare not equal, the result mask is all 0s. For the PCMPGTx instructions, if the signed value in the firstoperand is greater than the signed value in the second operand, the result mask is all 1s. If the value inthe first operand is less than or equal to the value in the second operand, the result mask is all 0s.By specifying the same register for both operands, PCMPEQx can be used to set the bits in an XMMregister to all 1s.Figure 4-10 on page 115 shows an example of a non-branching sequence that implements a two-waymultiplexer—one that is equivalent to the following sequence of ternary operators in C or C++:r0r1r2r3r4r5r6r7========a0a1a2a3a4a5a6a7>>>>>>>>b0b1b2b3b4b5b6b7????????a0a1a2a3a4a5a6a7::::::::b0b1b2b3b4b5b6b7Assuming xmm0 contains the vector a, and xmm1 contains the vector b, the above C sequence can beimplemented with the following assembler sequence:MOVQPCMPGTWPANDPANDNPOR154xmm3,xmm3,xmm0,xmm3,xmm0,xmm0xmm2xmm3xmm1xmm3;;;;aaar>>>=bbba??>>0xffff : 0a: 00 : bb ? a: b128-Bit Media and Scientific Programming24592—Rev.
3.13—July 2007AMD64 TechnologyIn the above sequence, PCMPGTW, PAND, PANDN, and POR operate, in parallel, on all fourelements of the vectors.Compare and Write Minimum or Maximum.••••PMAXUB—Packed Maximum Unsigned BytesPMINUB—Packed Minimum Unsigned BytesPMAXSW—Packed Maximum Signed WordsPMINSW—Packed Minimum Signed WordsThe PMAXUB and PMINUB instructions compare each of the 8-bit unsigned integer values in thefirst operand with the corresponding 8-bit unsigned integer values in the second operand. Theinstructions then write the maximum (PMAXUB) or minimum (PMINUB) of the two values for eachcomparison into the corresponding byte of the destination.The PMAXSW and PMINSW instructions perform operations analogous to the PMAXUB andPMINUB instructions, except on 16-bit signed integer values.4.5.8 LogicalThe vector-logic instructions perform Boolean logic operations, including AND, OR, and exclusiveOR.And• PAND—Packed Logical Bitwise AND• PANDN—Packed Logical Bitwise AND NOTThe PAND instruction performs a logical bitwise AND of the values in the first and second operandsand writes the result to the destination.The PANDN instruction inverts the first operand (creating a ones-complement of the operand), ANDsit with the second operand, and writes the result to the destination.
Table 4-9 shows an example.Table 4-9.Example PANDN Bit ValuesOperand1 BitOperand1 Bit(Inverted)Operand2 BitPANDNResult Bit1010100001110100128-Bit Media and Scientific Programming155AMD64 Technology24592—Rev. 3.13—July 2007Or• POR—Packed Logical Bitwise ORThe POR instruction performs a logical bitwise OR of the values in the first and second operands andwrites the result to the destination.Exclusive Or• PXOR—Packed Logical Bitwise Exclusive ORThe PXOR instruction performs a logical bitwise exclusive OR of the values in the first and secondoperands and writes the result to the destination. PXOR can be used to clear all bits in an XMMregister by specifying the same register for both operands.4.5.9 Save and Restore StateThese instructions save and restore the entire processor state for 128-bit media instructions.Save and Restore 128-Bit, 64-Bit, and x87 State• FXSAVE—Save XMM, MMX, and x87 State.• FXRSTOR—Restore XMM, MMX, and x87 State.The FXSAVE and FXRSTOR instructions save and restore the entire 512-byte processor state for 128bit media instructions, 64-bit media instructions, and x87 floating-point instructions.
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