Volume 1 Application Programming (794095), страница 44

Просмтор этого файла доступен только зарегистрированным пользователям. Но у нас супер быстрая регистрация: достаточно только электронной почты!

Текст из файла (страница 44)

These instructions convert floating-point data types inXMM registers or memory into different floating-point data types in XMM registers.••••CVTPS2PD—ConvertFloating-PointCVTPD2PS—ConvertFloating-PointCVTSS2SD—ConvertFloating-PointCVTSD2SS—ConvertFloating-PointPacked Single-Precision Floating-Point to Packed Double-PrecisionPacked Double-Precision Floating-Point to Packed Single-PrecisionScalar Single-Precision Floating-Point to Scalar Double-PrecisionScalar Double-Precision Floating-Point to Scalar Single-PrecisionThe CVTPS2PD instruction converts two single-precision floating-point values in the low-order 64bits of the second operand (an XMM register or a 64-bit memory location) to two double-precisionfloating-point values in the destination operand (an XMM register).The CVTPD2PS instruction converts two double-precision floating-point values in the second operandto two single-precision floating-point values in the low-order 64 bits of the destination.

The high-order64 bits in the destination XMM register are cleared to all 0s. If the result of the conversion is an inexactvalue, the value is rounded.162128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007AMD64 TechnologyThe CVTSS2SD instruction converts a single-precision floating-point value in the low-order 32 bits ofthe second operand to a double-precision floating-point value in the low-order 64 bits of thedestination. The high-order 64 bits in the destination XMM register are not modified.The CVTSD2SS instruction converts a double-precision floating-point value in the low-order 64 bitsof the second operand to a single-precision floating-point value in the low-order 64 bits of thedestination.

The three high-order doublewords in the destination XMM register are not modified. If theresult of the conversion is an inexact value, the value is rounded.Convert Floating-Point to XMM Integer. These instructions convert floating-point data types inXMM registers or memory into integer data types in XMM registers.••••CVTPS2DQ—Convert Packed Single-Precision Floating-Point to Packed Doubleword IntegersCVTPD2DQ—Convert Packed Double-Precision Floating-Point to Packed Doubleword IntegersCVTTPS2DQ—Convert Packed Single-Precision Floating-Point to Packed Doubleword Integers,TruncatedCVTTPD2DQ—Convert Packed Double-Precision Floating-Point to Packed DoublewordIntegers, TruncatedThe CVTPS2DQ and CVTTPS2DQ instructions convert four single-precision floating-point values inthe second operand to four 32-bit signed integer values in the destination.

For the CVTPS2DQinstruction, if the result of the conversion is an inexact value, the value is rounded, but for theCVTTPS2DQ instruction such a result is truncated (rounded toward zero).The CVTPD2DQ and CVTTPD2DQ instructions convert two double-precision floating-point valuesin the second operand to two 32-bit signed integer values in the destination.

The high-order 64 bits inthe destination XMM register are cleared to all 0s. For the CVTPD2DQ instruction, if the result of theconversion is an inexact value, the value is rounded, but for the CVTTPD2DQ instruction such a resultis truncated (rounded toward zero).For a description of 128-bit media instructions that convert in the opposite direction—integer tofloating-point—see “Convert Integer to Floating-Point” on page 139.Convert Floating-Point to MMX™ Integer. These instructions convert floating-point data types inXMM registers or memory into integer data types in MMX registers.••••CVTPS2PI—Convert Packed Single-Precision Floating-Point to Packed Doubleword IntegersCVTPD2PI—Convert Packed Double-Precision Floating-Point to Packed Doubleword IntegersCVTTPS2PI—Convert Packed Single-Precision Floating-Point to Packed Doubleword Integers,TruncatedCVTTPD2PI—Convert Packed Double-Precision Floating-Point to Packed Doubleword Integers,TruncatedThe CVTPS2PI and CVTTPS2PI instructions convert two single-precision floating-point values in thelow-order 64 bits of an XMM register or a 64-bit memory location to two 32-bit signed integer valuesin an MMX register.

For the CVTPS2PI instruction, if the result of the conversion is an inexact value,128-Bit Media and Scientific Programming163AMD64 Technology24592—Rev. 3.13—July 2007the value is rounded, but for the CVTTPS2PI instruction such a result is truncated (rounded towardzero).The CVTPD2PI and CVTTPD2PI instructions convert two double-precision floating-point values inan XMM register or a 128-bit memory location to two 32-bit signed integer values in an MMX register.For the CVTPD2PI instruction, if the result of the conversion is an inexact value, the value is rounded,but for the CVTTPD2PI instruction such a result is truncated (rounded toward zero).Before executing a CVTxPS2PI or CVTxPD2PI instruction, software should ensure that the MMXregisters are properly initialized so as to prevent conflict with their aliased use by x87 floating-pointinstructions.

This may require clearing the MMX state, as described in “Accessing Operands inMMX™ Registers” on page 188.For a description of 128-bit media instructions that convert in the opposite direction—integer in MMXregisters to floating-point in XMM registers—see “Convert MMX Integer to Floating-Point” onpage 139. For a summary of instructions that operate on MMX registers, see Chapter 5, “64-Bit MediaProgramming.”Convert Floating-Point to GPR Integer. These instructions convert floating-point data types inXMM registers or memory into integer data types in GPR registers.••••CVTSS2SI—Convert Scalar Single-Precision Floating-Point to Signed Doubleword or QuadwordIntegerCVTSD2SI—Convert Scalar Double-Precision Floating-Point to Signed Doubleword orQuadword IntegerCVTTSS2SI—Convert Scalar Single-Precision Floating-Point to Signed Doubleword orQuadword Integer, TruncatedCVTTSD2SI—Convert Scalar Double-Precision Floating-Point to Signed Doubleword orQuadword Integer, TruncatedThe CVTSS2SI and CVTTSS2SI instructions convert a single-precision floating-point value in thelow-order 32 bits of an XMM register or a 32-bit memory location to a 32-bit or 64-bit signed integervalue in a general-purpose register.

For the CVTSS2SI instruction, if the result of the conversion is aninexact value, the value is rounded, but for the CVTTSS2SI instruction such a result is truncated(rounded toward zero).The CVTSD2SI and CVTTSD2SI instructions convert a double-precision floating-point value in thelow-order 64 bits of an XMM register or a 64-bit memory location to a 32-bit or 64-bit signed integervalue in a general-purpose register. For the CVTSD2SI instruction, if the result of the conversion is aninexact value, the value is rounded, but for the CVTTSD2SI instruction such a result is truncated(rounded toward zero).For a description of 128-bit media instructions that convert in the opposite direction—integer in GPRregisters to floating-point in XMM registers—see “Convert GPR Integer to Floating-Point” onpage 140.

For a summary of instructions that operate on GPR registers, see Chapter 3, “GeneralPurpose Programming.”164128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007AMD64 Technology4.6.4 Data ReorderingThe floating-point data-reordering instructions unpack and interleave, or shuffle the elements of vectoroperands.Unpack and Interleave.

These instructions interleave vector elements from the high or low halves oftwo floating-point source operands.••••UNPCKHPS—Unpack High Single-Precision Floating-PointUNPCKHPD—Unpack High Double-Precision Floating-PointUNPCKLPS—Unpack Low Single-Precision Floating-PointUNPCKLPD—Unpack Low Double-Precision Floating-PointThe UNPCKHPx instructions copy the high-order two single-precision floating-point values(UNPCKHPS) or one double-precision floating-point value (UNPCKHPD) in the first and secondoperands and interleave them into the 128-bit destination. The low-order 64 bits of the source operandsare ignored.The UNPCKLPx instructions are analogous to their high-element counterparts except that they takeelements from the low quadword of each source vector and ignore elements in the high quadword.Depending on the hardware implementation, if the source operand for UNPCKHPx or UNPCKLPx isin memory, only the low 64 bits of the operand may be loaded.Figure 4-33 shows the UNPCKLPS instruction.

Характеристики

Список файлов книги