Volume 1 Application Programming (794095), страница 48
Текст из файла (страница 48)
Ifprocedures using both types of instructions are run in the same operating environment, separateservices routines should be provided for the exceptions of each type of instruction subset.4.10.1 General-Purpose ExceptionsThe sections below list general-purpose exceptions generated and not generated by 128-bit mediainstructions. For a summary of the general-purpose exception mechanism, see “Interrupts andExceptions” on page 86. For details about each exception and its potential causes, see “Exceptions andInterrupts” in Volume 2.Exceptions Generated.
The 128-bit media instructions can generate the following general-purposeexceptions:•••••••••••#DB—Debug Exception (Vector 1)#UD—Invalid-Opcode Exception (Vector 6)#NM—Device-Not-Available Exception (Vector 7)#DF—Double-Fault Exception (Vector 8)#SS—Stack Exception (Vector 12)#GP—General-Protection Exception (Vector 13)#PF—Page-Fault Exception (Vector 14)#MF—x87 Floating-Point Exception-Pending (Vector 16)#AC—Alignment-Check Exception (Vector 17)#MC—Machine-Check Exception (Vector 18)#XF—SIMD Floating-Point Exception (Vector 19)128-Bit Media and Scientific Programming177AMD64 Technology24592—Rev. 3.13—July 2007A device-not-available exception (#NM) can occur if an attempt is made to execute a 128-bit mediainstruction when the task switch bit (TS) of the control register (CR0) is set to 1 (CR0.TS = 1).An invalid-opcode exception (#UD) can occur if:•••a CPUID feature flag indicates that a feature is not supported (see “Feature Detection” onpage 176), oran FXSAVE or FXRSTOR instruction is executed when the floating-point software-emulation(EM) bit in control register 0 is set to 1 (CR0.EM = 1), ora SIMD floating-point exception occurs when the operating-system XMM exception support bit(OSXMMEXCPT) in control register 4 is cleared to 0 (CR4.OSXMMEXCPT = 0).Only the following 128-bit media instructions, all of which can access an MMX register, can cause an#MF exception:••Data Conversion: CVTPD2PI, CVTPS2PI, CPTPI2PD, CVTPI2PS, CVTTPD2PI, CVTTPS2PI.Data Transfer: MOVDQ2Q, MOVQ2DQ.For details on the system control-register bits, see “System-Control Registers” in Volume 2.
For detailson the machine-check mechanism, see “Machine Check Mechanism” in Volume 2.For details on #XF exceptions, see “SIMD Floating-Point Exception Causes” on page 178.Exceptions Not Generated. The 128-bit media instructions do not generate the following general-purpose exceptions:••••#DE—Divide-by-zero-error exception (Vector 0)Non-Maskable-Interrupt Exception (Vector 2)#BP—Breakpoint Exception (Vector 3)#OF—Overflow exception (Vector 4)•••••#BR—Bound-range exception (Vector 5)Coprocessor-segment-overrun exception (Vector 9)#TS—Invalid-TSS exception (Vector 10)#NP—Segment-not-present exception (Vector 11)#MC—Machine-check exception (Vector 18)For details on all general-purpose exceptions, see “Exceptions and Interrupts” in Volume 2.4.10.2 SIMD Floating-Point Exception CausesThe SIMD floating-point exception is the logical OR of the six floating-point exceptions (IE, DE, ZE,OE, UE, PE) that are reported (signalled) in the MXCSR register’s exception flags (“MXCSRRegister” on page 117).
Each of these six exceptions can be either masked or unmasked by software,using the mask bits in the MXCSR register.178128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007AMD64 TechnologyException Vectors. The SIMD floating-point exception is listed above as #XF (Vector 19) but itactually causes either an #XF exception or a #UD (Vector 6) exception, if an unmasked IE, DE, ZE,OE, UE, or PE exception is reported. The choice of exception vector is determined by the operatingsystem XMM exception support bit (OSXMMEXCPT) in control register 4 (CR4):••When CR4.OSXMMEXCPT = 1, a #XF exception occurs.When CR4.OSXMMEXCPT = 0, a #UD exception occurs.SIMD floating-point exceptions are precise. If an exception occurs when it is masked, the processorresponds in a default way that does not invoke the SIMD floating-point exception service routine.
If anexception occurs when it is unmasked, the processor suspends processing of the faulting instructionprecisely and invokes the exception service routine.Exception Types and Flags. SIMD floating-point exceptions are differentiated into six types, fiveof which are mandated by the IEEE 754 standard. These six types and their bit-flags in the MXCSRregister are shown in Table 4-10. The causes and handling of such exceptions are described below.Table 4-10. SIMD Floating-Point Exception FlagsException andMnemonicMXCSR Bit1Comparable IEEE 754ExceptionInvalid-operation exception (IE)0Invalid OperationDenormalized operation exception (DE)1noneZero-divide exception (ZE)2Division by ZeroOverflow exception (OE)3OverflowUnderflow exception (UE)4UnderflowPrecision exception (PE)5InexactNote:1.
See “MXCSR Register” on page 117 for a summary of each exception.The sections below describe the causes for the SIMD floating-point exceptions. The pseudocodeequations in these descriptions assume logical TRUE = 1 and the following definitions:MaxnormalThe largest normalized number that can be represented in the destination format.
This is equal tothe format’s largest representable finite, positive or negative value. (Normal numbers are describedin “Normalized Numbers” on page 128.)MinnormalThe smallest normalized number that can be represented in the destination format. This is equal tothe format’s smallest precisely representable positive or negative value with an unbiased exponentof 1.128-Bit Media and Scientific Programming179AMD64 Technology24592—Rev. 3.13—July 2007ResultinfiniteA result of infinite precision, which is representable when the width of the exponent and the widthof the significand are both infinite.ResultroundA result, after rounding, whose unbiased exponent is infinitely wide and whose significand is thewidth specified for the destination format.
(Rounding is described in “Floating-Point Rounding”on page 132.)Resultround, denormalA result, after rounding and denormalization. (Denormalization is described in “Denormalized(Tiny) Numbers” on page 128.)Masked and unmasked responses to the exceptions are described in “SIMD Floating-Point ExceptionMasking” on page 184. The priority of the exceptions is described in “SIMD Floating-Point ExceptionPriority” on page 182.Invalid-Operation Exception (IE). The IE exception occurs due to one of the attempted invalidoperations shown in Table 4-11.Table 4-11. Invalid-Operation Exception (IE) CausesOperationConditionAny Arithmetic Operation, andCVTPS2PD, CVTPD2PS, CVTSS2SD, CVTSD2SSA source operand is an SNaNMAXPS, MAXPD, MAXSS, MAXSDMINPS, MINPD, MINSS, MINSDCMPPS, CMPPD, CMPSS, CMPSDCOMISS, COMISDA source operand is a NaN (QNaN or SNaN)ADDPS, ADDPD, ADDSS, ADDSD, ADDSUBPS.ADDSUBPD, HADDPS, HADDPDSource operands are infinities with opposite signsSUBPS, SUBPD, SUBSS, SUBSD, ADDSUBPS,ADDSUBPD, HSUBPS, HSUBPDSource operands are infinities with same signMULPS, MULPD, MULSS, MULSDSource operands are zero and infinityDIVPS, DIVPD, DIVSS, DIVSDSource operands are both infinity or both zeroSQRTPS, SQRTPD, SQRTSS, SQRTSDSource operand is less than zero (except ±0, whichreturns ±0)Data conversion from floating-point to integer(CVTPS2PI, CVTPD2PI, CVTSS2SI, CVTSD2SI,CVTPS2DQ, CVTPD2DQ, CVTTPS2PI, CVTTPD2PI,CVTTPD2DQ, CVTTPS2DQ, CVTTSS2SI,CVTTSD2SI)Source operand is a NaN, infinite, or notrepresentable in destination data type180128-Bit Media and Scientific Programming24592—Rev.
3.13—July 2007AMD64 TechnologyDenormalized-Operand Exception (DE). The DE exception occurs when one of the sourceoperands of an instruction is in denormalized form, as described in “Denormalized (Tiny) Numbers”on page 128.Zero-Divide Exception (ZE). The ZE exception occurs when and instruction attempts to divide zerointo a non-zero finite dividend.Overflow Exception (OE).
The OE exception occurs when the value of a rounded floating-pointresult is larger than the largest representable normalized positive or negative floating-point number inthe destination format. Specifically:OE = Resultround > MaxnormalAn overflow can occur through computation or through conversion of higher-precision numbers tolower-precision numbers.Underflow Exception (UE). The UE exception occurs when the value of a rounded, non-zerofloating-point result is too small to be represented as a normalized positive or negative floating-pointnumber in the destination format. Such a result is called a tiny number, associated with the “PrecisionException (PE)” described immediately below.If UE exceptions are masked by the underflow mask (UM) bit, a UE exception occurs only if thedenormalized form of the rounded result is imprecise.
Specifically:UE =((UM=0 and (Resultround < Minnormal) or((UM=1 and (Resultround, denormal ) != Resultinfinite)Underflows can occur, for example, by taking the reciprocal of the largest representable number, or byconverting small numbers in double-precision format to a single-precision format, or simply throughrepeated division. The flush-to-zero (FZ) bit in the MXCSR offers additional control of underflowsthat are masked. See “MXCSR Register” on page 117 for details.Precision Exception (PE).
The PE exception, also called the inexact-result exception, occurs when arounded floating-point result differs from the infinitely precise result and thus cannot be representedprecisely in the destination format. This exception is caused by—among other things—rounding ofunderflow or overflow results according to the rounding control (RC) field in the MXCSR, asdescribed in “Floating-Point Rounding” on page 132.If an overflow or underflow occurs and the OE or UE exceptions are masked by the overflow mask(OM) or underflow mask (UM) bit, a PE exception occurs only if the rounded result (for OE) or thedenormalized form of the rounded result (for UE) is imprecise. Specifically:PE =((Resultround, denormal or Resultround ) != Resultinfinite) or(OM=1 and (Resultround > Maxnormal)) or(UM=1 and (Resultround, denormal < Minnormal))Software that does not require exact results normally masks this exception.128-Bit Media and Scientific Programming181AMD64 Technology24592—Rev.
3.13—July 20074.10.3 SIMD Floating-Point Exception PriorityFigure 4-12 on page 182 shows the priority with which the processor recognizes multiple,simultaneous SIMD floating-point exceptions and operations involving QNaN operands. Eachexception type is characterized by its timing, as follows:••Pre-Computation—an exception that is recognized before an instruction begins its operation.Post-Computation—an exception that is recognized after an instruction completes its operation.For masked (but not unmasked) post-computation exceptions, a result may be written to thedestination, depending on the type of exception.
Operations involving QNaNs do not necessarily causeexceptions, but the processor handles them with the priority shown in Table 4-12 relative to thehandling of exceptions.Table 4-12. Priority of SIMD Floating-Point ExceptionsPriorityException or Operation1Invalid-operation exception (IE) when accessingSNaN operand2Operation involving a QNaN operand13456TimingPre-Computation—Any other type of invalid-operation exception (IE)Pre-ComputationZero-divide exception (ZE)Pre-ComputationDenormalized operation exception (DE)Pre-ComputationOverflow exception (OE)Post-ComputationUnderflow exception (UE)Post-ComputationPrecision (inexact) exception (PE)Post-ComputationNote:1. Operations involving QNaN operands do not, in themselves, cause exceptions but they arehandled with this priority relative to the handling of exceptions.Figure 4-38 on page 183 shows the prioritized procedure used by the processor to detect and reportSIMD floating-point exceptions.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
