Volume 1 Application Programming (794095), страница 49
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Each of the two types of exceptions—pre-computation and postcomputation—is handled independently and completely in the sequence shown. If there are nounmasked exceptions, the processor responds to masked exceptions. Because of this two-step process,up to two exceptions—one pre-computation, one post-computation—can be caused by a singleinstruction.182128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007For EachExceptionTypeAMD64 TechnologyFor EachVectorElementTest ForPre-ComputationExceptionsSet MXCSRException FlagsAnyUnmasked Exceptions?YesNoFor EachExceptionTypeFor EachVectorElementTest ForPre-ComputationExceptionsSet MXCSRException FlagsYesAnyUnmasked Exceptions?NoInvoke ExceptionService RoutineAnyMasked Exceptions?YesDefaultResponseNoContinue ExecutionFigure 4-38.513-188.epsSIMD Floating-Point Detection Process128-Bit Media and Scientific Programming183AMD64 Technology24592—Rev.
3.13—July 20074.10.4 SIMD Floating-Point Exception MaskingThe six floating-point exception flags have corresponding exception-flag masks in the MXCSRregister, as shown in Table 4-13.Table 4-13.SIMD Floating-Point Exception MasksException Maskand MnemonicMXCSR BitComparable IEEE 754ExceptionInvalid-operation exception mask (IM)7Invalid OperationDenormalized-operand exception mask (DM)8noneZero-divide exception mask (ZM)9Division by ZeroOverflow exception mask (OM)10OverflowUnderflow exception mask (UM)11UnderflowPrecision exception mask (PM)12InexactEach mask bit, when set to 1, inhibits invocation of the exception handler for that exception andinstead causes a default response.
Thus, an unmasked exception is one that invokes its exceptionhandler when it occurs, whereas a masked exception continues normal execution using the defaultresponse for the exception type. During power-on initialization, all exception-mask bits in the MXCSRregister are set to 1 (masked).Masked Responses. The occurrence of a masked exception does not invoke its exception handlerwhen the exception condition occurs. Instead, the processor handles masked exceptions in a defaultway, as shown in Table 4-14 on page 185.184128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007AMD64 TechnologyTable 4-14.
Masked Responses to SIMD Floating-Point ExceptionsExceptionOperation1Any of the following, in which one or both operands is anSNaN:• Addition (ADDPS, ADDPD, ADDSS, ADDSD,ADDSUBPD, ADDSUBPS, HADDPS, HADDPD), or• Subtraction (SUBPS, SUBPD, SUBSS, SUBSD,ADDSUBPD, ADDSUBPS, HSUBPD, HSUBPS), or• Multiplication (MULPS, MULPD, MULSS, MULSD), or• Division (DIVPS, DIVPD, DIVSS, DIVSD), or• Square-root (SQRTPS, SQRTPD, SQRTSS, SQRTSD),or• Data conversion of floating-point to floating-point(CVTPS2PD, CVTPD2PS, CVTSS2SD, CVTSD2SS).Invalidoperationexception (IE)Processor Response2Return a QNaN, based onthe rules in Table 4-5 onpage 130.• Addition of infinities with opposite sign (ADDPS, ADDPD,ADDSS, ADDSD, ADDSUBPS, ADDSUBPD, HADDPD,HADDPS), or• Subtraction of infinities with same sign (SUBPS, SUBPD,SUBSS, SUBSD, ADDSUBPS, ADDSUBPD, HSUBPS,HSUBPD), orReturn the floating-pointindefinite value.• Multiplication of zero by infinity (MULPS, MULPD,MULSS, MULSD), or• Division of zero by zero or infinity by infinity (DIVPS,DIVPD, DIVSS, DIVSD), or• Square-root in which the operand is non-zero negative(SQRTPS, SQRTPD, SQRTSS, SQRTSD).Any of the following, in which one or both operands is aNaN:• Maximum or Minimum (MAXPS, MAXPD, MAXSS,MAXSD MINPS, MINPD, MINSS, MINSD)Return second sourceoperand.Compare is unordered or notCompare, in which one orReturn mask of all 1s.equalboth operands is a NaN(CMPPS, CMPPD, CMPSS,All other comparesReturn mask of all 0s.CMPSD).Note:1.
For complete details about operations, see “SIMD Floating-Point Exception Causes” on page 178.2. In all cases, the processor sets the associated exception flag in MXCSR. For details about number representation,see “Floating-Point Number Representation” on page 127 and “Floating-Point Number Encodings” on page 130.3. This response does not comply with the IEEE 754 standard, but it offers higher performance.128-Bit Media and Scientific Programming185AMD64 Technology24592—Rev.
3.13—July 2007Table 4-14. Masked Responses to SIMD Floating-Point Exceptions (continued)ExceptionInvalidoperationexception (IE)Operation1Processor Response2Sets the result in rFLAGS toOrdered or unordered scalar compare, in which one or both “unordered.”operands is a NaN (COMISS, COMISD, UCOMISS,Clear the overflow (OF), signUCOMISD).(SF), and auxiliary carry(AF) flags in rFLAGS.Data conversion from floating-point to integer, in whichsource operand is a NaN, infinity, or is larger than therepresentable value of the destination (CVTPS2PI,CVTPD2PI, CVTSS2SI, CVTSD2SI, CVTPS2DQ,CVTPD2DQ, CVTTPS2PI, CVTTPD2PI, CVTTPD2DQ,CVTTPS2DQ, CVTTSS2SI, CVTTSD2SI).Return the integer indefinitevalue.Denormalizedoperandexception (DE)One or both operands is denormalReturn the result using thedenormal operand(s).Zero-divideexception (ZE)Divide (DIVx) zero with non-zero finite dividendReturn signed infinity, withsign bit = XOR of theoperand sign bits.Overflow when roundingmode = round to nearestOverflow when roundingmode = round toward +∞Overflowexception (OE)Overflow when roundingmode = round toward -∞Sign of result is positiveReturn +∞.Sign of result is negativeReturn –∞.Sign of result is positiveReturn +∞.Sign of result is negativeReturn finite negativenumber with largestmagnitude.Sign of result is positiveReturn finite positivenumber with largestmagnitude.Sign of result is negativeReturn –∞.Sign of result is positiveReturn finite positivenumber with largestmagnitude.Sign of result is negativeReturn finite negativenumber with largestmagnitude.MXCSR flush-to-zero (FZ)bit = 0Set PE flag and returndenormalized result.MXCSR flush-to-zero (FZ)bit = 1Set PE flag and return zero,with sign of true result.3Overflow when roundingmode = round toward 0Underflowexception (UE)Inexact denormalized resultNote:1.
For complete details about operations, see “SIMD Floating-Point Exception Causes” on page 178.2. In all cases, the processor sets the associated exception flag in MXCSR. For details about number representation,see “Floating-Point Number Representation” on page 127 and “Floating-Point Number Encodings” on page 130.3. This response does not comply with the IEEE 754 standard, but it offers higher performance.186128-Bit Media and Scientific Programming24592—Rev. 3.13—July 2007AMD64 TechnologyTable 4-14.
Masked Responses to SIMD Floating-Point Exceptions (continued)Operation1ExceptionPrecisionexception (PE)Inexact normalized ordenormalized resultProcessor Response2Without OE or UE exceptionReturn rounded result.With masked OE or UEexceptionRespond as for OE or UEexception.With unmasked OE or UEexceptionRespond as for OE or UEexception, and invoke SIMDexception handler.Note:1.
For complete details about operations, see “SIMD Floating-Point Exception Causes” on page 178.2. In all cases, the processor sets the associated exception flag in MXCSR. For details about number representation,see “Floating-Point Number Representation” on page 127 and “Floating-Point Number Encodings” on page 130.3. This response does not comply with the IEEE 754 standard, but it offers higher performance.Unmasked Responses.
If the processor detects an unmasked exception, it sets the associatedexception flag in the MXCSR register and invokes the SIMD floating-point exception handler. Theprocessor does not write a result or change any of the source operands for any type of unmaskedexception. The exception handler must determine which exception occurred (by examining theexception flags in the MXCSR register) and take appropriate action.In all cases of unmasked exceptions, before calling the exception handler, the processor examines theCR4.OSXMMEXCPT bit to see if it is set to 1. If it is set, the processor calls the #XF exception (vector19).
If it is cleared, the processor calls the #UD exception (vector 6). See “System-Control Registers”in Volume 2 for details.For details about the operations that can cause unmasked exceptions, see “SIMD Floating-PointException Causes” on page 178 and Table 4-14 on page 185.Using NaNs in IE Diagnostic Exceptions. Both SNaNs and QNaNs can be encoded with manydifferent values to carry diagnostic information. By means of appropriate masking and unmasking ofthe invalid-operation exception (IE), software can use signaling NaNs to invoke an exception handler.Within the constraints imposed by the encoding of SNaNs and QNaNs, software may freely assign thebits in the significand of a NaN.
See “Not a Number (NaN)” on page 129 for format details.For example, software can pre-load each element of an array with a signaling NaN that encodes thearray index. When an application accesses an uninitialized array element, the invalid-operationexception is invoked and the service routine can identify that element. A service routine can storedebug information in memory as the exceptions occur. The routine can create a QNaN that referencesits associated debug area in memory. As the program runs, the service routine can create a differentQNaN for each error condition, so that a single test-run can identify a collection of errors.128-Bit Media and Scientific Programming187AMD64 Technology4.1124592—Rev.
3.13—July 2007Saving, Clearing, and Passing State4.11.1 Saving and Restoring StateIn general, system software should save and restore 128-bit media state between task switches or otherinterventions in the execution of 128-bit media procedures. Virtually all modern operating systemsrunning on x86 processors—like Windows NT®, UNIX, and OS/2—are preemptive multitaskingoperating systems that handle such saving and restoring of state properly across task switches,independently of hardware task-switch support. However, application procedures are also free to saveand restore 128-bit media state at any time they deem useful.Software running at any privilege level may save and restore 128-bit media state by executing theFXSAVE instruction, which saves not only 128-bit media state but also x87 floating-point state.Alternatively, software may use multiple move instructions for saving only the contents of selected128-bit media data registers, or the STMXCSR instruction for saving the MXCSR register state.
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