Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 60
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The construct “@hhh…h” withinthe file specifies the hexadecimal address to use as the starting address. Subsequentdata is loaded starting at that memory address. Note that the “h” specifies hexadecimal digits only. There is no length or base format specified. There may be severaladdress specifications allowing several sub-blocks of memory to be loaded while therest remains untouched.The format for data in the file is either binary or hexadecimal numbers only. Thelength and base is not specified. The numbers are separated by white space.
Verilogcomments are allowed.Verilog also has access to a set of I/O system function calls that essentially duplicate several of the C language file I/O functions. They are:GFormal SyntaxDefinitionThis formal syntax specfication is provided in BNF. This information, starting insection G.2 and continuing through the end of this sppendix, is reprinted from IEEEStandard 1364-2001 “IEEE Standard Verilog Hardware Description Language Reference Manual (LRM)”, Copyright © 2001 by the Institute of Electrical and Electronics Engineers, Inc (IEEE).
The IEEE disclaims any responsibility or liabilityresulting from the placement and use in this publication. This information isreprinted with the permission of the IEEE.G.1 Tutorial Guide to Formal SyntaxSpecificationThe formal syntax notation will be introduced through an example — in this caseExample G.1, an edge triggered D flip flop, dEdgeFF. Using this example we willdescribe the formal syntax of a module definition.To this point, we have, by example, demonstrated that a module definition usescertain keywords (“module”, “endmodule”) and has other entities associated with it(“ports”, “instantiations”, etc.). The formal syntax for a module is:The Verilog Hardware Description Language340module dEdgeFF(output q,input clock, data);regwirereset;q, qBar, r, s, r1, si;initial beginreset = 1;#20 reset = 0;endnor #10a (q, qBar, r, reset);norb (qBar, q, s),c (s, r, clock, s1),d (s1, s, data),e (r, r1, clock),f(r1,s1,r);endmoduleExample G.1 An Edge-Triggered Flip Flopmodule_declarationmodule_keyword module_identifier [ module_parameter_port_list][list_of_ports];{ module_item }endmodule| module_keyword module_identifier [ module_parameter_port_list][list_of_ports_declarations];{ non_port_module_item }endmodulemodule_keywordmodule|macromoduleIn plain words, the module construct (“module_declaration”) is defined by a“module_keyword,” followed by the “module_identifier.” The name is optionally followed by a list of parameters (the “[ ]” indicates an optional item), an optional list ofpoerts, and then by a “;”.
Next come zero or more module items (the “{ }” indicateszero or more) followed by the “endmodule” keyword. The module_keyword is thekeyword “module” or “macromodule” and the “module_identifier” is the name of the341module. A definition of this can be found under “identifier.” Examples of all of theseitems can be seen in Example G.1.As a key, the construct before theis the item to be defined. The line with thestarts the definition of the construct (later we will see that “|” indicates an alternate definition).
Any other items in regular text are constructs that are defined elsewhere. Finally, bold text indicates literal text — text like “module” or “;” that willappear directly in the description. Typically, these are keywords and language punctuation. Some items are listed with the first part being italic and the rest being regulartext. The italic part adds extra semantic information to the regular text item. The itemto be used is found under the definition of the regular text item.We still need to define the syntax construct items.
Below are the rest of the definitions for a module. In some cases, the text “…” is used to indicate that there are morealternatives but that due to space or expediency, they won’t be list and discussed here.All syntax construct items used in the normal text of the book are keyed to the identically named items in the Appendix.More of the formal syntax for a module:module_identifieridentifierThe Verilog Hardware Description Language342A module is named using a module_identifier. The full definition of identifier is notincluded here. However, the later appendix has the full definition.Now let’s consider the ports.
Above we see that a module has an optionallist_of_ports. Below we see that a list_of_ports is one or more comma-separated portslisted within parentheses. Thus if there are no ports to the module (after all, they’reoptional), then nothing is specified — not even a null “()”. However, if there is at leastone port, then parentheses are used to contain the list of comma-separated ports.list_of_ports(port {,port})A port is an optional port_expression which in turn is either a port_reference or aconcatenation of port_references. A port_reference is either a port_identifier (whichis actually an identifier), a bit-select of a port_identifier (the second alternative in thelist), or a part-select of port_identifier (the third alternative). The items in the bitand part-selects are constants indicating which bits are to be used. The selects areenclosed in literal square brackets and the constants of a part-select are separated by aliteral colon.port[ port_expression ]port_expressionport_reference| {port_reference {, port reference} }port_referenceport_identifier| port_identifier [ constant_expression ]| port_identifier [ range_expression ]Going further with the module definition, we see that it also includes zero, one, ormore module_items.
One item is the module_or_generate_item which is itself a longlist of alternatives — some of which we see in Example G.1. For instance, the Example contains gate instantiations, initial constructs, and always constructs. We also seeother familiar items — gate and module instantiations, and continuous assignments.module_itemmodule_or_generate_item|port_declaration|generated_instantiation|local_parameter_declaration|parameter_declaration343module_or_generate_itemmodule_or_generate_item_declaration|continuous_assignment|gate_instantiation|initial_construct|always_constructReferences: register specifications E.1; IDENTIFIERS B.5, G.10G.2 Source textG.2.1 Library source textlibrary_text ::= {library_descriptions }library_descriptions ::=library_declaration| include_statement| config_declarationlibrary_declaration ::=library library_identifier file_path_spec [ {, file_path_spec } ][ -incdir file_path_spec [ {, file_path_spec } ];file_path_spec ::= file_pathinclude_statement ::= include <file_path_spec> ;G.2.2 Configuration source textconfig_declaration ::=config config_identifier;design_statement{config_rule_statement}endconfigdesign_statement ::= design {[library_identifier.]cell_identifier } ;config_rule_statement ::=default_clause liblist_clause| inst_clause liblist_clause| inst_clause use_clause| cell_clause liblist_clause| cell_clause use_clausedefault_clause ::= defaultinst_clause ::= instance inst_nameIEEE Std 1364-2001, Copyright © 2001, IEEE.
All rights reserved344The Verilog Hardware Description Languageinst_name ::= topmodule_identifier{.instance_identifier}cell_clause ::= cell [ library_identifier.]cell_identifierliblist_clause ::= liblist [{library_identifier}]use_clause ::= use [library_identifier.]cell_identifier[:config]G.2.3 Module and primitive source textsource_text ::= { description }description ::=module_declaration| udp_declarationmodule_declaration ::={ attribute_instance } module_keyword module_identifier [module_parameter_port_list ][ list_of_ports ]; { module_item }endmodule| { attribute_instance } module_keyword module_identifier [module_parameter_port_list ][ list_of_port_declarations ]; { non_port_module_item }endmodulemodule_keyword ::= module | macromoduleG.2.4 Module parameters and portsmodule_parameter_port_list ::= # (parameter_declaration {, parameter_declaration})list_of_ports ::= (port {, port})list_of_port_declarations ::=(port_declaration {, port_declaration } )|()port ::=[ port_expression ]| port_identifier ( [ port_expression ] )port_expression ::=port_reference| { port_reference {, port_reference } }port_reference ::=port_identifier| port_identifier [ constant_expression ]| port_identifier [ range_expression ]port_declaration ::={attribute_instance} inout_declarationIEEE Std 1364-2001, Copyright © 2001, IEEE.
All rights reserved345| {attribute_instance} input_declaration| {attribute_instance} output_declarationG.2.5 Module itemsmodule_item ::=module_or_generate_item| port_declaration ;| { attribute_instance } generated_instantiation| { attribute_instance } local_parameter_declaration| { attribute_instance } parameter_declaration| { attribute_instance } specify_block| { attribute_instance } specparam_declarationmodule_or_generate_item ::={ attribute_instance } module_or_generate_item_declaration| { attribute_instance } parameter_override| { attribute_instance } continuous_assign| { attribute_instance } gate_instantiation| { attribute_instance } udp_instantiation| { attribute_instance } module_instantiation| { attribute_instance } initial_construct| { attribute_instance } always_constructmodule_or_generate_item_declaration ::=net_declaration| reg_declaration| integer_declaration| real_declaration| time_declaration| realtime_declaration| event_declaration| genvar_declaration| task_declaration| function_declarationon_port_module_item ::={ attribute_instance } generated_instantiation| { attribute_instance } local_parameter_declaration| { attribute_instance } module_or_generate_item| { attribute_instance } parameter_declaration| { attribute_instance } specify_block| { attribute_instance } specparam_declarationIEEE Std 1364-2001, Copyright © 2001, IEEE.
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