Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 66
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Seeprocedural continuous assign379Rrandom system task 168, 170, 336example of 119readmemb system task 337readmemh system task 124, 337registers (reg) 329relational operators 79See also operator table 315repeatexample of 76, 82, 94formal definition 83intra-assignment 134,233keyword 78resistive MOS gatesSee nmos switch level primitivesrnmos switch level primitivesSee gate types 327rpmos switch level primitivesSee gate types 327Sscalar 329scalared 165scheduled behavior 195scope 102, 133example 104sensitivity list 40, 212, 218sequential blocksSee begin-end blockssigned expression 319simulation cycle 216simulatorhow it works 214scheduling algorithm 216, 220simulation cycle 216Sm abbreviation 259small 259, 260small capacitor 259specify block 187example of 187specparamexample of 187St abbreviation 259stime 336stop system task 336strength0 260strength1 260strengths 251, 256ambiguity 263conversion to 1, 0, x, z 263displaying 260example of display 257example of specifications 257formal definition 260gate types supported 260reduction through resistivegates 262resolving ambiguous values 264table of 259strings 311strobe system task 335strong 256, 259strong drive 259strong0 259strongl 259structural modeling 157Su abbreviation 259supply 259supply drive 259supply0 259table of net types 166supplyl 259table of net types 166switch level modeling 251synthesisbehavioral 198explicit FSM 53finite state machines 53implicit FSM 56logical don’t care 44, 55pipeline 57restrictions 66rules 41testbench approach 8using always 40synthesis restrictions# 37(non)blocking assignments 51flip flop specifications 50latch specifications 49logical don’t care 46repeat 46unknown (x) 39synthesis rules 13,18synthesizable subset 35system tasks and functions 333Ttablebitwise AND 321bitwise OR 321bitwise XNOR 321bitwise XOR 321BUFIF1 gate function 182delay values 184delay/precision specification 185expression bit length 322380four-value logic gates 323four-valued AND 162gate and switch level primitives 161,252gates supporting strengths 260intra-assignment events 134items in formal syntax 341net types and modeling 166parts of a number 310strength reduction 262strength specifications 259task and function comparison 92timescale compiler directive 185UPD shorthand 247Verilog keywords 313Verilog operators 315wand and wire 164table as keyword 240See also user-defined primitives 240task enableformal definition 96tasks 91a structural view 100contrast to function 93contrast to functions 92example of 94formal definition 93text macroSee `definethread of control 73, 198time 336advancement in behavioralmodels 74advancement in logic models 158advancement near a black hole 221See also timing modelsspecifying units 185time variables 329, 331timing model 189, 211gate level 158, 212procedural 74, 213transfer gates 256tritable of net types 166tri0table of net types 166tri1table of net types 166triandtable of net types 166triortable of net types 166triregexample of 253The Verilog Hardware Description Languagetable of net types 166See also netsUundefined 162update event 216user-defined primitives 239combinational 240edge sensitive 244example of 240level sensitive 243mixing edge and level sensitive 246shorthand notation 246Vvalue set 162vector 329vectored 165VHDL 169Wwait 116contrast to event control 121contrast to while 84, 120example of 119formal definition 117wandexamples of 164table of net types 166We abbreviation 259weak 259weak drive 259weak0 259weak1 259whilecontrast to wait 84, 120example of 83formal definition 83white space 309wiretable of net types 166wortable of net types 166write system task 333Xx 162in synthesis 44, 55See multi-value truth tables 323xnorSee gate types 325See table of operators 315xor381See gate types 324See table of operators 315Zz 162in synthesis 52See multi-value truth tables 323zero-time 220.
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