Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 64

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All rights reservedThe Verilog Hardware Description Language366G.9.2 Function callsconstant_function_call ::= function_identifier { attribute_instance }( constant_expression { , constant_expression } )function_call ::=hierarchical_function_identifier{ attribute_instance }( expression { , expression } )genvar_function_call ::= genvar_function_identifier { attribute_instance }(constant_expression { , constant_expression } )system_function_call ::= system_function_identifier[ ( expression { , expression } ) ]G.9.3 Expressionsbase_expression ::= expressionconditional_expression ::= expressionl ? { attribute_instance } expression2 :expression3constant_base_expression ::= constant_expressionconstant_expression ::=constant_primary| unary_operator { attribute_instance } constant_primary| constant_expression binary_operator { attribute_instance } constant_expression| constant_expression ? { attribute_instance } constant_expression :constant_expression| stringconstant_mintypmax_expression ::=constant_expression| constant_expression: constant_expression : constant_expressionconstant_range_expression ::=constant_expression| msb_constant_expression: 1sb_constant_expression| constant_base_expression +: width_constant_expression| constant_base_expression -: width_constant_expressiondimension_constant_expression ::= constant_expressionexpression1 ::= expressionexpression2 ::= expressionexpression3 ::= expressionexpression ::=primary| unary_operator { attribute_instance } primary| expression binary_operator { attribute_instance } expression| conditional_expression| stringIEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reserved3671sb_constant_expression ::= constant_expressionmintypmax_expression::=expression| expression : expression : expressionmodule_path_conditional_expression ::= module_path_expression ? {attribute_instance }module_path_expression : module_path_expressionmodule_path_expression ::=module_path_primary| unary_module_path_operator { attribute_instance } module_path_primary| module_path_expression binary_module_path_operator { attribute_instance }module_path_expression| module_path_conditional_expressionmodule_path_mintypmax_expression::=module_path_expression| module_path_expression : module_path_expression : module_path_expressionmsb_constant_expression ::= constant_expressionrange_expression ::=expression| msb_constant_expression: 1sb_constant_expression| base_expression +: width_constant_expression| base_expression -: width_constant_expressionwidth_constant_expression ::= constant_expressionG.9.4 Primariesconstant_primary ::=constant_concatenation| constant_function_call| ( constant_mintypmax_expression )| constant_multiple_concatenation| genvar_identifier| number| parameter_identifier| specparam_identifiermodule_path_primary ::=number| identifier| module_path_concatenation| module_path_multiple_concatenation| function_call| system_function_callIEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reservedThe Verilog Hardware Description Language368| constant_function_call| ( module_path_mintypmax_expression)primary ::=number| hierarchical_identifier| hierarchical_identifier [ expression ] { [ expression ] }| hierarchical_identifier [ expression ] { [ expression ] } [ range_expression ]| hierarchical_identifier [ range_expression ]| concatenation| multiple_concatenation| function_call| system_function_call| constant_function_call| ( mintypmax_expression )G.9.5 Expression left-side valuesnet_1value ::=hierarchical_net_identifier| hierarchical_net_identifier [ constant_expression ] { [ constant_expression ] }| hierarchical_net_identifier [ constant_expression ] {[ constant_expression ] } [constant_range_expression ]| hierarchical_net_identifier [ constant_range_expression ]| net_concatenationvariable_1value ::=hierarchical_variable_identifier| hierarchical_variable_identifier [ expression ] { [ expression ] }| hierarchical_variable_identifier [ expression ] { [ expression ] } [range_expression ]| hierarchical_variable_identifier [ range_expression ]| variable_concatenationG.9.6 Operatorsunary_operator ::=+ | - |! |~ | &| ~&||| ~| | ^| ~^| ^~binary_operator ::=+ | -|*| /| % | == | != | === | !== | &&| || | **| < | <= | > | >= | &| | | ^ | ^~ | ~^ | >> | << | >>> | <<<unary_module_path_operator ::=!|~ |& | ~& | | | ~| | ^ | ~^ | ^~binary_module_path_operator ::=IEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reserved369==|!= | &&| ||| & ||| ^ | ^~ | ~^G.9.7 Numbersnumber ::=decimal_number| octal_number| binary_number| hex_number| real_numberreal_number<Superscript>1 ::=unsigned_number unsigned_number| unsigned_number [ unsigned_number ] exp [ sign ] unsigned_numberexp ::=e | Edecimal_number ::=unsigned_number| [ size ] decimal_base unsigned_number| [ size ] decimal_base x_digit { _ }| [ size ] decimal_base z_digit { _ }binary_number ::= [ size ] binary_base binary_valueoctal_number ::= [ size ] octal_base octal_valuehex_number ::= [ size ] hex_base hex_valuesign::= + | size ::= non_zero_unsigned_numbernon_zero_unsigned_number<Superscript>1 ::= non_zero_decimal_digit { _ |decimal_digit}unsigned_number<Superscript>1 ::= decimal_digit { _ | decimal_digit}binary_value<Superscript>1 ::= binary_digit { _ | binary_digit}octal_value<Superscript>1 ::= octal_digit { _ | octal_digit}hex_value<Superscript>1 ::= hex_digit {_ | hex_digit}decimal_base<Superscript>1 ::='[s|S]d| '[s|S]Dbinary_base<Superscript>1 ::= '[s|S]b| '[s|S]Boctal_base<Superscript>1 ::='[s|S]o| '[s|S]Ohex_base<Superscript>1 ::= '[s|S]h | '[s|S]Hnon_zero_decimal_digit ::=1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9decimal_digit ::=0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9binary_digit ::= x_digit | z_digit | 0 |1octal_digit ::= x_digit | z_digit | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7hex_digit ::=x_digit | z_digit | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9|a|b|c|d|e|f|A|B|C|D|E|Fx_digit ::= x | XIEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reservedThe Verilog Hardware Description Language370z_digit::= z | Z | ?G.9.8 Stringsstring ::= " { Any_ASCII_Characters_except_new_line } "G.10 GeneralG.10.1 Attributesattribute_instance ::= (* attr_spec { , attr_spec } *)attr_spec ::=attr_name = constant_expression| attr_nameattr_name ::= identifierG.10.2 Commentscomment ::=one_line_comment| block_commentone_line_comment ::= // comment_text \nblock_comment ::= /* comment_text */comment_text ::= { Any_ASCII_character }G.10.3 Identifiersarrayed_identifier ::=simple_arrayed_identifier| escaped_arrayed_identifierblock_identifier ::= identifiercell_identifier ::= identifierconfig_identifier ::= identifierescaped_arrayed_identifier ::= escaped_identifier [ range ]escaped_hierarchical_identifier<Superscript>4 ::=escaped_hierarchical_branch{.simple_hierarchical_branch | .escaped_hierarchical_branch }escaped_identifier ::=\ {Any_ASCII_character_except_white_space} white_spaceevent_identifier ::= identifierfunction_identifier ::= identifierIEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reserved371gate_instance_identifier ::= arrayed_identifiergenerate_block_identifier ::= identifiergenvar_function_identifier ::= identifier /* Hierarchy disallowed */genvar_identifier ::= identifierhierarchical_block_identifier ::= hierarchical_identifierhierarchical_event_identifier ::= hierarchical_identifierhierarchical_function_identifier ::= hierarchical_identifierhierarchical_identifier ::=simple_hierarchical_identifier| escaped_hierarchical_identifierhierarchical_net_identifier ::= hierarchical_identifierhierarchical_variable_identifier ::= hierarchical_identifierhierarchical_task_identifier ::= hierarchical_identifieridentifier ::=simple_identifier| escaped_identifierinout_port_identifier ::= identifierinput_port_identifier ::= identifierinstance_identifier ::= identifierlibrary_identifier ::= identifiermemory_identifier ::= identifiermodule_identifier ::= identifiermodule_instance_identifier ::= arrayed_identifiernet_identifier ::= identifieroutput_port_identifier ::= identifierparameter_identifier ::= identifierport_identifier ::= identifierreal_identifier ::= identifiersimple_arrayed_identifier ::= simple_identifier [ range ]simple_hierarchical_identifier<Superscript>3 ::=simple_hierarchical_branch [ .escaped_identifier ]simple_identifier<Superscript>2 ::= [ a-zA-Z_ ] { [ a-zA-Z0-9_$ ] }specparam_identifier ::= identifiersystem_function_identifier<Superscript>5 ::= $[ a-zA-Z0-9_$ ]{ [ a-zA-Z0-9_$ ] }system_task_identifier<Superscript>5 ::= $[ a-zA-Z0-9_$ ]{ [ a-zA-Z0-9_$ ] }task_identifier ::= identifierterminal_identifier ::= identifiertext_macro_identifier ::= simple_identifiertopmodule_identifier ::= identifierudp_identifier ::= identifierudp_instance_identifier ::= arrayed_identifierIEEE Std 1364-2001, Copyright © 2001, IEEE.

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