Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 63

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All rights reservedThe Verilog Hardware Description Language360| pulsestyle_ondetect list_of_path_outputs ;showcancelled_declaration ::=showcancelled list_of_path_outputs ;| noshowcancelled list_of_path_outputs ;G.8.2 Specify path declarationspath_declaration ::=simple_path_declaration ;| edge_sensitive_path_declaration ;| state_dependent_path_declaration ;simple_path_declaration ::=parallel_path_description = path_delay_value| full_path_description = path_delay_valueparallel_path_description ::=( specify_input_terminal_descriptor [ polarity_operator ] =>specify_output_terminal_descriptor )full_path_description ::=( list_of_path_inputs [ polarity_operator ] *> list_of_path_outputs )list_of_path_inputs ::=specify_input_terminal_descriptor { , specify_input_terminal_descriptor }list_of_path_outputs ::=specify_output_terminal_descriptor { , specify_output_terminal_descriptor }G.8.3 Specify block terminalsspecify_input_terminal_descriptor ::=input_identifier| input_identifier [ constant_expression ]| input_identifier [ range_expression ]specify_output_terminal_descriptor ::=output_identifier| output_identifier [ constant_expression ]| output_identifier [ range_expression ]input_identifier ::= input_port_identifier | inout_port_identifieroutput_identifier ::= output_port_identifier | inout_port_identifierG.8.4 Specify path delayspath_delay_value ::=list_of_path_delay_expressions| ( list_of_path_delay_expressions )IEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reserved361list_of_path_delay_expressions ::=t_path_delay_expression| trise_path_delay_expression , tfall_path_delay_expression| trise_path_delay_expression , tfall_path_delay_expression ,tz_path_delay_expression| t01_path_delay_expression , t10_path_delay_expression ,t0z_path_delay_expression ,tz1_path_delay_expression , t1z_path_delay_expression ,tz0_path_delay_expression| t01_path_delay_expression , t10_path_delay_expression ,t0z_path_delay_expression ,tz1_path_delay_expression , t1z_path_delay_expression ,tz0_path_delay_expressiont0x_path_delay_expression, tx1_path_delay_expression ,t1x_path_delay_expression ,tx0_path_delay_expression , txz_path_delay_expression ,tzx_path_delay_expressiont_path_delay_expression ::= path_delay_expressiontrise_path_delay_expression ::= path_delay_expressiontfall_path_delay_expression ::= path_delay_expressiontz_path_delay_expression ::= path_delay_expressiont01_path_delay_expression ::= path_delay_expressiont10_path_delay_expression: = path_delay_expressiont0z_path_delay_expression: = path_delay_expressiontz1_path_delay_expression ::= path_delay_expressiont1z_path_delay_expression ::= path_delay_expressiontz0_path_delay_expression ::= path_delay_expressiont0x_path_delay_expression ::= path_delay_expressiontx1_path_delay_expression ::= path_delay_expressiont1x_path_delay_expression ::= path_delay_expressiontx0_path_delay_expression ::= path_delay_expressiontxz_path_delay_expression ::= path_delay_expressiontzx_path_delay_expression ::= path_delay_expressionpath_delay_expression ::= constant_mintypmax_expressionedge_sensitive_path_declaration ::=parallel_edge_sensitive_path_description = path_delay_value| full_edge_sensitive_path_description = path_delay_valueparallel_edge_sensitive_path_description ::=( [ edge_identifier ] specify_input_terminal_descriptor =>specify_output_terminal_descriptor [ polarity_operator ] :data_source_expression)full_edge_sensitive_path_description ::=( [ edge_identifier ] list_of_path_inputs *>IEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reservedThe Verilog Hardware Description Language362list_of_path_outputs [ polarity_operator ] : data_source_expression )data_source_expression ::= expressionedge_identifier ::= posedge | negedgestate_dependent_path_declaration ::=if ( module_path_expression) simple_path_declaration| if ( module_path_expression ) edge_sensitive_path_declaration| ifnone simple_path_declarationpolarity_operator ::= + | -G.8.5 System timing checksG.8.5.1 System timing check commandssystem_timing_check ::=$setup_timing_check| $hold _timing_check| $setuphold_timing_check| $recovery_timing_check| $removal_timing_check| $recrem_timing_check| $skew_timing_check| $timeskew_timing_check| $fullskew_timing_check| $period_timing_check| $width_timing_check| $nochange_timing_check$setup_timing_check ::=$setup( data_event , reference_event , timing_check_limit [ , [ notify_reg ] ] ) ;$hold _timing_check ::=$hold ( reference_event , data_event , timing_check_limit [ , [ notify_reg ] ] ) ;$setuphold_timing_check ::=$setuphold ( reference_event , data_event , timing_check_limit ,timing_check_limit[ , [ notify_reg ] [ , [ stamptime_condition ] [ , [checktime_condition ][ , [ delayed_reference ] [ , [ delayed_data ] ] ] ] ] ] ) ;$recovery_timing_check ::=$recovery ( reference_event , data_event , timing_check_limit [ , [ notify_reg ]]);$removal_timing_check ::=$removal ( reference_event , data_event , timing_check_limit [ , [ notify_reg ]]);IEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reserved363$recrem_timing_check ::=$recrem ( reference_event , data_event , timing_check_limit ,timing_check_limit[, [ notify_reg ] [, [ stamptime_condition ] [ , [checktime_condition ][, [ delayed_reference ] [, [ delayed_data ] ] ] ] ] ] ) ;$skew_timing_check ::=$skew ( reference_event , data_event , timing_check_limit [, [ notify_reg ] ] ) ;$timeskew_timing_check ::=$timeskew ( reference_event , data_evet , timing_check_limit[, [ notify_reg ] [, [ event_based_flag ] [, [ remain_active_flag]]]]);$fullskew_timing_check ::=$fullskew ( reference_event , data_event , timing_check_limit ,timing_check_limit[ , [ notify_reg ] [, [ event_based_flag ] [, [ remain_active_flag]]]]);$period_timing_check ::=$period ( controlled_reference_event , timing_check_limit [ , [ notify_reg ] ]) ;$width_timing_check ::=$width ( controlled_reference_event , timing_check_limit ,threshold [, [ notify_reg ] ] ) ;$nochange_timing_check ::=$nochange ( reference_event , data_event , start_edge_offset ,end_edge_offset [ , [ notify_reg ] ] ) ;G.8.5.2 System timing check command argumentschecktime_condition ::= mintypmax_expressioncontrolled_reference_event ::= controlled_timing_check_eventdata_event ::= timing_check_eventdelayed_data ::=terminal_identifier| terminal_identifier [ constant_mintypmax_expression ]delayed_reference ::=terminal_identifier| terminal_identifier [ constant_mintypmax_expression ]end_edge_offset ::= mintypmax_expressionevent_based_flag ::= constant_expressionnotify_reg ::= variable_identifierreference_event ::= timing_check_eventremain_active_flag ::= constant_mintypmax_expressionIEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reserved364The Verilog Hardware Description Languagestamptime_condition ::= mintypmax_expressionstart_edge_offset ::= mintypmax_expressionthreshold ::=constant_expressiontiming_check_limit ::= expressionG.8.5.3 System timing check event definitionstiming_check_event ::=[timing_check_event_control] specify_terminal_descriptor [ &&&timing_check_condition ]controlled_timing_check_event ::=timing_check_event_control specify_terrninal_descriptor [ &&&timing_check_condition ]tirning_check_event_control ::=posedge| negedge| edge_control_specifierspecify_terminal_descriptor ::=specify_input_terminal_descriptor| specify_output_terminal_descriptoredge_control_specifier ::= edge [ edge_descriptor [ , edge_descriptor ] ]edge_descriptor<Superscript>1 ::=0110z_or_x zero_or_onezero_or_one z_or_xzero_or_one ::= 0 1z_or_x ::= x | X | z | Ztiming_check_condition ::=scalar_timing_check_condition| (scalar_timing_check_condition )IEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reserved365scalar_timing_check_condition ::=expression| ~ expression| expression == scalar_constant| expression === scalar_constant| expression != scalar_constant| expression !== scalar_constantscalar_constant ::=1'b0 |1'b1 |1'B0 |1'B1 |'b0| 'bl|'B0| 'B1|1 | 0G.9 ExpressionsG.9.1 Concatenationsconcatenation ::= { expression {, expression } }constant_concatenation ::= { constant_expression {, constant_expression } }constant_multiple_concatenation ::= { constant_expression constant_concatenation }module_path_concatenation ::= {module_path_expression {,module_path_expression}}module_path_multiple_concatenation ::= { constant_expressionmodule_path_concatenation}multiple_concatenation ::= {constant_expression concatenation}net_concatenation ::= {net_concatenation_value {, net_concatenation_value } }net_concatenation_value ::=hierarchical_net_identifier| hierarchical_net_identifier [ expression ] { [ expression ] }| hierarchical_net_identifier [ expression ] { [ expression ] } [ range_expression ]| hierarchical_net_identifier [ range_expression ]| net_concatenationvariable_concatenation ::= { variable_concatenation_value {,variable_concatenation_value }}variable_concatenation_value ::=hierarchical_variable_identifier| hierarchical_variable_identifier [ expression ] { [ expression ] }| hierarchical_variable_identifier [ expression ] { [ expression ] } [range_expression ]| hierarchical_variable_identifier [ range_expression ]| variable_concatenationIEEE Std 1364-2001, Copyright © 2001, IEEE.

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