Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 62

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All rights reservedThe Verilog Hardware Description Language352, enable_terminal)n_input_gate_instance ::= [ name_of_gate_instance ] ( output_terminal ,input_terminal { , input_terminal } )n_output_gate_instance ::= [ name_of_gate_instance ] ( output_terminal { ,output_terminal } , input_terminal )pass_switch_instance::= [ name_of_gate_instance ] ( inout_terminal , inout_terminal )pass_enable_switch_instance ::= [ name_of_gate_instance ] ( inout_terminal ,inout_terminal , enable_terminal )pull_gate_instance ::= [ name_of_gate_instance ] ( output_terminal )name_of_gate_instance ::= gate_instance_identifier [ range ]GA.2 Primitive strengthspulldown_strength ::=( strength0 , strength1 )| ( strength1 , strength0 )| ( strength0 )pullup_strength ::=( strength0 , strength1 )| ( strength1 , strength0 )| ( strength1 )G.4.3 Primitive terminalsenable_terminal ::= expressioninout_terminal ::=net_lvalueinput_terminal ::= expressionncontrol_terminal ::= expressionoutput_terminal ::= net_lvaluepcontrol_terminal ::= expressionG.4.4 Primitive gate and switch typescmos_switchtype ::= cmos | rcmosenable_gatetype ::= bufif0 | bufif1 | notif0 | notif1mos_switchtype ::= nmos | pmos | rnmos | rpmosn_input_gatetype ::= and | nand | or | nor | xor | xnorn_output_gatetype ::= buf | notpass_en_switchtype ::= tranif0 | tranif1 | rtranif1 | rtranif0pass_switchtype ::= tran | rtranIEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reserved353G.5 Module and generated instantiationG.5.1 Module instantiationmodule_instantiation ::=module_identifier [ parameter_value_assignment ]module_instance { , module_instance } ;parameter_value_assignment ::= # ( list_of_parameter_assignments )list_of_parameter_assignments ::=ordered_parameter_assignment { , ordered_parameter_assignment } |named_parameter_assignment { , named_parameter_assignment }ordered_parameter_assignment ::= expressionnamed_parameter_assignment ::= parameter_identifier ( [ expression ] )module_instance ::= name_of_instance ( [ list_of_port_connections ] )name_of_instance ::= module_instance_identifier [ range ]list_of_port_connections ::=ordered_port_connection { , ordered_port_connection }| named_port_connection { , named_port_connection }ordered_port_connection ::= { attribute_instance } [ expression ]named_port_connection ::= { attribute_instance } .port_identifier ( [ expression ] )G.5.2 Generated instantiationgenerated_instantiation ::= generate { generate_item } endgenerategenerate_item_or_null ::= generate_item | ;IEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reservedThe Verilog Hardware Description Language354generate_item ::=generate_conditional_statement| generate_case_statement| generate_loop_statement| generate_block| module_or_generate_itemgenerate_conditional_statement ::=if ( constant_expression ) generate_item_or_null [ else generate_item_or_null ]generate_case_statement ::= case ( constant_expression )genvar_case_item { genvar_case_item } endcasegenvar_case_item ::= constant_expression { , constant_expression } :generate_item_or_null | default [ : ] generate_item_or_nullgenerate_loop_statement ::= for ( genvar_assignment ; constant_expression ;genvar_assignment )begin : generate_block_identifier { generate_item } endgenvar_assignment ::= genvar_identifier = constant_expressiongenerate_block ::= begin [ : generate_block_identifier ] { generate_item } endG.6 UDP declaration and instantiationG.6.1 UDP declarationudp_declaration ::={ attribute_instance } primitive udp_identifier ( udp_port_list ) ;udp_port_declaration { udp_port_declaration}udp_bodyendprimitive| { attribute_instance } primitive udp_identifier ( udp_declaration_port_list ) ;udp_bodyendprimitiveG.6.2 UDP portsudp_port_list ::= output_port_identifier, input_port_identifier { ,input_port_identifier}udp_declaration_port_list ::=udp_output_declaration , udp_input_declaration { , udp_input_declaration }udp_port_declaration ::=udp_output_declaration ;| udp_input_declaration ;IEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reserved355| udp_reg_declaration ;udp_output_declaration ::={ attribute_instance } output port_identifier| { attribute_instance } output reg port_identifier [ = constant_expression ]udp_input_declaration ::= { attribute_instance } input list_of_port_identifiersudp_reg_declaration ::= { attribute_instance } reg variable_identifierG.6.3 UDP bodyudp_body ::= combinational_body | sequential_bodycombinational_body ::=table combinational_entry { combinational_entry } endtablecombinational_entry ::= level_input_list : output_symbol ;sequential_body ::= [ udp_initial_statement ] table sequential_entry {sequential_entry } endtableudp_initial_statement ::= initial output_port_identifier = init_val ;init_val ::= 1'b0 | 1'b1 | 1'bx | 1'bX | 1'B1 | 1'Bl | 1'Bx | 1'BX | 1 | 0sequential_entry ::= seq_input_list : current_state : next_state ;seq_input_list ::= level_input_list | edge_input_listlevel_input_list ::=level_symbol { level_symbol }edge_input_list ::= { level_symbol } edge_indicator { level_symbol }edge_indicator ::= ( level_symbol level_symbol ) | edge_symbolcurrent_state ::= level_symbolnext_state ::= output_symbol | output_symbol ::= 0 | 1 | x | Xlevel_symbol ::= 0 | 1 | x | X | ? | b | Bedge_symbol ::= r | R | f | F | p | P | n | N | *G.6.4 UDP instantiationudp_instantiation ::= udp_identifier [ drive_strength ] [ delay2 ]udp_instance { , udp_instance } ;udp_instance ::= [ name_of_udp_instance ] ( output_terminal, input_terminal{ , input_terminal } )name_of_udp_instance ::= udp_instance_identifier [ range ]G.7 Behavioral statementsG.7.1 Continuous assignment statementscontinuous_assign ::= assign [ drive_strength ] [ delay3 ] list_of_net_assignments ;IEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reservedThe Verilog Hardware Description Language356list_of_net_assignments ::= net_assignment { , net_assigmnent }net_assignment ::= net_lvalue = expressionG.7.2 Procedural blocks and assignmentsinitial_construct ::= initial statementalways_construct ::= always statementblocking_assignment ::= variable_lvalue = [ delay_or_event_control ] expressionnonblocking_assigmnent ::=variable_lvalue<= [ delay_or_event_control ] expressionprocedural_continuous_assignments ::=assign variable_assignment| deassign variable_lvalue| force variable_assignment| force net_assignment| release variable_lvalue| release net_lvaluefunction_blocking_assignment ::= variable_lvalue = expressionfunction_statement_or_null ::=function_statement| { attribute_instance } ;G.7.3 Parallel and sequential blocksfunction_seq_block ::= begin [ : block_identifier{ block_item_declaration } ] { function_statement} endvariable_assignment ::= variable_lvalue = expressionpar_block ::= fork [ : block_identifier{ block_item_declaration } ] { statement } joinseq_block ::= begin [ : block_identifier{ block_item_declaration } ] { statement } endG.7.4 Statementsstatement ::={ attribute_instance } blocking_assignment ;| { attribute_instance } case_statement| { attribute_instance } conditional_statement| { attribute_instance } disable_statement| { attribute_instance } event_trigger| { attribute_instance } loop_statement| { attribute_instance } nonblocking_assignment ;| { attribute_instance } par_blockIEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reserved357| { attribute_instance } procedural_continuous_assignments ;| { attribute_instance } procedural_timing_control_statement| { attribute_instance } seq_block| { attribute_instance } system_task_enable| { attribute_instance } task_enable| { attribute_instance } wait_statementstatement_or_null ::=statement| { attribute_instance } ;function_statement ::={ attribute_instance } function_blocking_assignment ;| { attribute_instance } function_case_statement| { attribute_instance } function_conditional_statement| { attribute_instance } function_loop_statement| { attribute_instance } function_seq_block| { attribute_instance } disable_statement| { attribute_instance } system_task_enableG.7.5 Timing control statementsdelay_control ::=# delay_value| # ( mintypmax_expression )delay_or_event_control ::=delay_control| event_control| repeat ( expression ) event_controldisable_statement ::=disable hierarchical_task_identifier ;| disable hierarchical_block_identifier ;event_control ::=@ event_identifier| @ ( event_expression )| @*| @ (*)event_trigger ::=-> hierarchical_event_identifier ;event_expression ::=expression| hierarchical_identifier| posedge expression| negedge expressionIEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reservedThe Verilog Hardware Description Language358| event_expression or event_expression| event_expression , event_expressionprocedural_timing_control_statement ::=delay_or_event_control statement_or_nullwait_statement ::=wait ( expression ) statement_or_nullG.7.6 Conditional statementsconditional_statement ::=if ( expression )statement_or_null [ else statement_or_null ]| if_else_if_statementif_else_if_statement ::=if ( expression ) statement_or_null{ else if ( expression ) statement_or_null }[ else statement_or_null ]function_conditional_statement ::=if ( expression ) function_statement_or_null[ else function_statement_or_null ]| function_if_else_if_statementfunction_if_else_if_statement ::=if ( expression ) function_statement_or_null{ else if ( expression ) function_statement_or_null}[ else function_statement_or_null ]G.7.7 Case statementscase_statement ::=case ( expression )case_item { case_item } endcase| casez ( expression )case_item { case_item } endcase| casex ( expression )case_item { case_item } endcasecase_item ::=expression { , expression } : statement_or_null| default [ : ] statement_or_nullfunction_case_statement ::=case ( expression )function_case_item { function_case_item } endcase| casez ( expression )IEEE Std 1364-2001, Copyright © 2001, IEEE.

All rights reserved359function_case_item { function_case_item } endcase| casex ( expression )function_case_item { function_case_item } endcasefunction_case_item ::=expression { , expression } : function_statement_or_null| default [ : ] function_statement_or_nullG.7.8 Looping statementsfunction_loop_statement ::=forever function_statement| repeat ( expression ) function_statement| while ( expression ) function_statement| for ( variable_assignment ; expression ; variable_assignment )function_statementloop_statement ::=forever statement| repeat ( expression ) statement| while ( expression ) statement| for ( variable_assignment ; expression ; variable_assignment )statementG.7.9 Task enable statementssystem_task_enable ::= system_task_identifier [ ( expression { , expression } ) ] ;task_enable ::= hierarchical_task_identifier [ ( expression { , expression } ) ] ;G.8 Specify sectionG.8.1 Specify block declarationspecify_block ::= specify { specify_item } endspecifyspecify_item ::=specparam_declaration| pulsestyle_declaration| showcancelled_declaration| path_declaration| system_timing_checkpulsestyle_declaration ::=pulsestyle_onevent list_of_path_outputs ;IEEE Std 1364-2001, Copyright © 2001, IEEE.

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