Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 58
Текст из файла (страница 58)
Real and integer operandsmay be signed. If any bit is unknown,the relation is ambiguous and the resultwill be unknown.<=Less than orequalDetermines relative valueRegister and net operands are treated asunsigned. Real and integer operandsmay be signed. If any bit is unknown,the relation is ambiguous and the resultwill be unknown.!Logical negation Unary Complement&&Logical ANDConverts a non-zero value (TRUE) intozero; a zero value (FALSE) into one;and an ambiguous truth value into x.ANDs two logical Used as a logical connective in, forvalues.instance, if statements.
e.g. if ((a > b)&&(c<d)).317Table 3.1 Verilog Operators||==!=Logical ORORs two logicalvalues.Used as a logical connective in, forinstance, if statements, e.g. if ((a > b) ||(c < d)).Logical equality Compares twoRegister and net operands are treated asvalues for equality unsigned. Real and integer operandsmay be signed. If any bit is unknown,the relation is ambiguous and the resultwill be unknown.Logical inequal- Compares twoRegister and net operands are treated asityvalues for inequal- unsigned. Real and integer operandsitymay be signed.
If any bit is unknown,the relation is ambiguous and the resultwill be unknown.===Case equalityThe bitwise comparison includes comCompares twovalues for equality parison of x and z values. All bits mustmatch for equality. The result is eitherTRUE or FALSE.!==Case inequalityThe bitwise comparison includes comCompares twovalues for inequal- parison of x and z values. Any bit differityence produces inequality. The result iseither TRUE or FALSE.~Bitwise negation Complementseach bit in theoperand&Bitwise ANDProduces the bit- See truth table belowwise AND of twooperands.|Bitwise ORProduces the bit- See truth table belowwise inclusive ORof two operands.^Bitwise XORProduces the bit- See truth table belowwise exclusive ORof two operands.^~ or ~^EquivalenceProduces the bitwise exclusiveNOR of twooperands&Unary reduction Produces the sin- Unary reduction and binary bitwisegle bit AND of all operators are distinguished by syntax.ANDof the bits of theoperand.Each bit of the operand is complemented.
The complement of x is x.See truth table belowThe Verilog Hardware Description Language318Table 3.1 Verilog Operators~ &Unary reduction Produces the sin- Unary reduction and binary bitwiseNANDgle bit NAND of operators are distinguished by syntax.all of the bits ofthe operand.IUnary reduction Produces the sin- Unary reduction and binary bitwiseORgle bit inclusiveoperators are distinguished by syntax.OR of all of thebits of the operand.~|Unary reduction Produces the sin- Unary reduction and binary bitwiseNORgle bit NOR of all operators are distinguished by syntax.of the bits of theoperand.^Unary reduction Produces the sin- Unary reduction and binary bitwiseXORgle bit XOR of all operators are distinguished by syntax.of the bits of theoperand.~^ or ^~Unary reduction Produces the sin- Unary reduction and binary bitwiseXNORgle bit XNOR of operators are distinguished by syntax.all of the bits ofthe operand.<<Left shiftShift the leftVacated bit positions are filled withoperand left byzerosthe number of bitpositions specifiedby the right operand>>Right shiftVacated bit positions are filled withShift the leftoperand right by zerosthe number of bitpositions specifiedby the right operand<<<Arithmetic shiftleftShift the leftThis is the same as left shift (<<).operand left bythe number of bitpositions specifiedby the right operand.319Table 3.1 Verilog Operators>>>Arithmetic shiftrightShift the leftoperand right bythe number of bitpositions specifiedby the right operand.?:ConditionalAssign one of two condExpr ? trueExpr : falseExpr.
If convalues based ondExpr is TRUE, the trueExpr is theexpressionresult of the operator. If condExpr isFALSE, the falseExpr is the result. Ifthe condExpr is ambiguous, then bothtrueExpr and falseExpr expressions arecalculated and the result is produced in abitwise fashion. For each bit, if bothexpression bits are one, the result is one.If both are zero, the result is zero. Otherwise, the resulting bit is x. The operator is right associative.If the left operand is signed, the vacatedbit positins will be filled with copies ofthe sign bit.
Otherwise it will fill withzeros.Convert tosignedThis is actually a system function callthat takes a name and returns it as asigned value. This allows the unsignedvalue m to be treated in an expression asif it was a signed valueConvert tounsignedThis is actually a system function callthat takes a name and returns it as anunsigned value.
This allows the signedvalue m to be treated in an expression asif it was an unsigned valueIf all of the operands of an expression are signed, then signed operations are performed. If any operand is not signed, then unsigned operations are used. Theandoperations above is used, for instance, to change anunsigned operand into a signed one so that an expression can be calculated in a signedmanner.320The Verilog Hardware Description LanguageC.2 Operator PrecedenceThe operator precedences are shown below.
The top of the table is the highest precedence, and the bottom is the lowest. Operators listed on the same line have the sameprecedence. All operators associate left to right in an expression (except ?:). Parentheses can be used to change the precedence or clarify the situation.
When in doubt, useparentheses. They are easier to read, and reread!Highest precedenceLowest precedence321C.3 Operator Truth Tables322The Verilog Hardware Description LanguageC.4 Expression Bit LengthsIn the following table, L(i) refers to the length in bits of operand i.DVerilog Gate TypesD.1 Logic GatesThese gates all have one scalar output and any number of scalar inputs. When instantiating one of these modules, the first parameter is the output and the rest are inputs.Zero, one or two delays may be specified for the propagation times. Strengths may bespecified on the outputs.324The Verilog Hardware Description Language325D.2 BUF and NOT GatesThese gates have one or more scalar outputs and one scalar input. The input is listedlast on instantiation.
Zero, one, or two delays may be specified. Strengths may bespecified on the outputs.326The Verilog Hardware Description LanguageD.3 BUFIF and NOTIF GatesThese gates model three-state drivers. Zero, one, two, or three delays may be specified. Each of the gates has one output, one data input, and one control input. Oninstantiation, the ports are listed in that order. (L indicates 0 or z; H indicates 1 or z)327D.4 MOS GatesThese gates model NMOS and PMOS transistors. The “r” versions model NMOSand PMOS transistors with significantly higher resistivity when conducting.
Theresistive forms reduce the driving strength from input to output. The nonresistiveforms only reduce the supply strength to a strong strength. See Table 10.7. Drivestrengths may not be specified for these gates.Each gate has one scalar output, one scalar data input, and one scalar control input,and on instantiation, are listed in that order. (L indicates 0 or z; H indicates 1 or z)328The Verilog Hardware Description LanguageD.5 Bidirectional GatesThe following gates are true bidirectional transmission gates: tran, tranif1, tranif0,rtran, rtranif1, and rtranif0. Each of these has two scalar inout terminals. The tranifand rtranif gates have a control input which is listed last on instantiation.The rise delay indicates the turn-on delay for the pass device and the fall delayindicates the turn-off delay.D.6 CMOS GatesCMOS gates represent the typical situation where nmos and pmos transistors arepaired together to form a transmission gate.
The first terminal is the data output, thesecond is the data input, the third is the n-channel control, and the last is the p-channel control. The cmos gate is a relatively low impedance device. The rcmos version hasa higher impedance when conducting.D.7 Pullup and Pulldown GatesThese are single output gates that drive pull strength values (the default) onto theoutput net. Pullup drives a logic one and pulldown drives a logic zero.
The strengthmay be specified.ERegisters,Memories, Integers,and TimeE.1 RegistersRegisters are abstractions of storage devices found in digital systems. They are definedwith the reg keyword and are optionally given a size (or bit width). The default size isone. Thus:reg tempBit;defines a single bit register named tempBit, whilereg [15:0] tempNum;defines a 16-bit register named tempNum. Single-bit registers are termed scalar, andmultiple-bit registers are termed vector. The bit width specification gives the name ofthe most significant bit first (in this case, 15) and the least significant bit last.The register could have been declared asreg [0:15] tempNum;with the only difference being that the most significant bit is named (numbered) 0.
Ofcourse, all the other bits are differently numbered. Further, the register can bedeclared as signedThe Verilog Hardware Description Language330regsigned[15:0] tempNum;indicating that when used in an expression, it is to be treated as a signed (2’s complement) number.The general form of a register specification is:reg_declarationreg [signed] [range] list_of_variable_identifiers;list_of_variable_identifiersvariable_type { , variable_type }variable_typevariable_identifier [ = constant_expression]| variable_identifier dimension {dimension}variable_identifieridentifierdimension[dimension_constant_expression : dimension_constant_expression ]Either a single bit, or several contiguous bits of a vector register (or net) can beaddressed and used in an expression.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
