Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 55
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The goal of this appendix is to provide far more help andguidance than we could in Chapter 1. This appendix contains tutorial help for thebeginning student and questions appropriate for use with an introductory course indigital systems design or computer architecture. The sections here are referenced fromthe sections of Chapter 1.Some of the questions assume that the reader has access to a Verilog simulator —the one included on the book’s CD will suffice.
A few of the questions assume accessto a synthesis tool; limited access to one is available through the CD. Finally, thebook’s CD includes copies of the books examples; retrieve them from there to avoidretyping.A.1 Structural DescriptionsThe questions in this section accompany Section 1.1.2. The first two include adetailed presentation of how to develop a simple Verilog description, including a discussion of common mistakes.
The questions following assume more familiarity with ahardware description language and simulator.The Verilog Hardware Description Language294A.1Write a Verilog description of the logicdiagram shown in Figure A. 1. Thislogic circuit implements the Booleanfunctionwhich you canprobably see by inspection of the Kmap. Since this is the first from-scratchdescription, the discussion section hasfar more help.Do This — Write a module specificationfor this logic circuit.
The module will nothave inputs or outputs. Use primitives gates(AND, OR, and NOT), connect them withwires, and include an initial statement to fullytest your circuit. To produce from B, add a NOT gate (inverter) to the above diagram. Specify that NOT gates have a delay of 1 time unit and the others have delays of2 time units. Oh, and try not to look at the answer below! If you’re not sure what todo, read on.Discussion: The first thing to write is the module header and name — give it anyname you wish. Next, break the description down into the individual gates, assigningdistinct names to the wires connecting the gates.
Now write the gate instantiationsand specify the ports for interconnecting them. A gate is instantiated as shown here:and#5 myFirstAnd (q, r, s);Here an AND gate with delay five, instance name myFirstAnd, and ports q, r, and s isdefined. Which connection is first in the list? The output; q it the output and the others are inputs. Finish instantiating the gates.In answering the question, you might have written the following module description. Clearly, you probably used a different name for the module (it’s top here) andalso for the gate instance names (e.g., g1).
The delay specification, which is optionalwhen specifying gate instantiations, is required in the description because the problemstatement asked for it. There are other ways to start writing this problem.module top;not#1 g1(d,b);and#2 g2 (e, d, a);or#2 g3(f,c,d);endmoduleThis description will not parse; some of the identifiers have not been declared.Some?295Do This — Explain which ones? Why not the others? There are no declarations inthis description, so why don’t all of the identifiers produce an error?The reason is that an output of a primitive gate is declared as a wire by default.Thus, identifiers d, e, and f are all defaulted to be of type wire.
a, b, and c are notdeclared and will thus cause errors. Why is the output of a primitive gate defaulted tobe a wire? Real combinational logic gates are connected to wires. In the Verilog language, new values are either driven on nets (wires are the default type of net) or loadedinto registers. Primitive gates always drive wires.Now continue the example by declaring the gate inputs (a, b, and c) to be registers.This will allow us to assign values to them in an initial statement and to test the output of our logic function. We could add the following declarations.wire d, e, f;reg a, b, c;But remember that the wire declaration is not needed because gate outputs default towire declarations.
The following description would parse without errors.module top;rega, b, c;notandorendmodule#1 g1 (d,b);#2 g2 (e, d, a);#2 g3 (f,c,d);But, this description wouldn’t do much except parse correctly. The goal is to simulate the design and convince yourself that the specification performs the logic functionthat you expect. Now we need to specify a set of inputs (called test vectors) so that wecan simulate the circuit and observe its output.Do This — write an initial block that will provide several different inputs to thesegates and display all values in the circuit. The block should be part of the top module.The ordered series of inputs that we will put into our design will be (a, b, c): 100,110,010, 011. This is a fairly extensive test set, even though it does not test every inputcombination.Discussion:To use the registers that we put in the description for the gate inputs,we need to write an initial block — registers can only be loaded by assignment statements in initial and always blocks.
We’ll use an initial block since these are often usedto provide test vector inputs.Here’s our first try. Following the statements, the first three put 100 on the inputs(a, b, c). The next assignment changes b to make the input 110. The fifth assignmentThe Verilog Hardware Description Language296changes a to make the input 010, and the last assignment makes the input 011.
Thatis the sequence of inputs we want, but alas this specification will not work.initial begina = l;b = 0;c = 0;b = l;a = 0;c = l;endDo This — Explain why this initial block will not work.Discussion: There are two errors here. One error is there is no means of displayingthe output when the inputs change. Let’s add astatement to display thedata to the screen whenever any value changes. Additionally, we will have the simulation time reported. In our case we will use the statement:"a=%b, b=%b, c=%b, d=%b, e=%b, f=%b", a, b, c, d, e, f);The monitor statement is not just a print statement. It will cause a printing of thequoted string when executed but then it will continue to monitor for changes on anyof the input identifiers (a, b, c, d, e, and f here), printing the quoted string when anyone changes. Only one of thesestatements can be active at the same time.
Ifone is reached while another is active, the new one cancels the old.The second error is more fundamental. The error is that the only input value thegates will see is the last one: 011. The simulation didn’t stop to let the intermediatevalues flow through the gates. Here’s how to think about how the simulator works.
Atthe start of the simulation, all values in the system (both nets and registers) have thevalue x (i.e., unknown). The initial and always blocks start executing in an arbitraryorder. In this system, we only have one initial block; it runs, making all of the assignments, and then it stops with a = 0, b = 1, and c = 1. When the initial block stops, thegates notice that their inputs have changed and they calculate their output values.
Theother input combinations are never seen by the gates.Indeed, if we simulated our current version of the module shown below we wouldget the simulation trace showing only the final inputs and output. Not cool.297module top;wired, e, f;rega, b, c;notandor#1 g1(d,b);#2 g2(e, a, d);#2 g 3 ( f , e , c ) ; / /initial begina = 1;b = 0;c = 0;b = 1;a = 0;c = 1;#20endendmodule"a=%b, b=%b, c=%b, d=%b, e=%b, f=%b\n",a,b,c,d,e,f);// initialization// first change of input// second change of input// third change of input// this tells the simulator to stopHere is the simulated output showing the values in the circuit.
The first value on theline is the time at which the values occur. The first line shows the inputs valid at time0, the output of the not gate (d) changes one time unit later, and the output of g2 (e)and g3 (f) change at time 2. Note that the value of 1 on c causes f to change at time 2.We don’t have to wait for the output of the not gate to propagate through gate g2 andg3.0 a=0, b=l, c=l, d=x, e=x, f=x1 a=0, b=l, c=l, d=0, e=x, f=x2 a=0, b=l, c=l, d=0, e=0, f=lBack to our problem: no delay was used in the assignment of the registers, and theywere all assigned (in order, from top to bottom) during the same time. We need toadd delay statements that will stop the execution of the initial block long enough sothat the gates can produce their outputs.
The new initial block could be:The Verilog Hardware Description Language298initial begina = 1;b = 0;c = 0;#2 b = 1;#2 a = 0;#2 c = 1;"a=%b, b=%b, c=%b, d=%b, e=%b, f=%b\n",a, b, c, d, e, f);// initialization//first change of input// second change of input// third change of input#20endAlthough this does add delay to the circuit and allows the values to propagate intothe circuit, it doesn’t allow enough time, as these results show:0 a=l, b=0, c=0, d=x, e=x, f=x1a=l, b=0, c=0, d=l, e=x, f=x2 a=l, b=l, c=0, d=l, e=x, f=x3 a=l,b=l,c=0,d=0,e=0,f=x4 a=0,b=l,c=0,d=0,e=0,f=x5 a=0,b=l,c=0,d=0,e=0,f=06 a=0,b=l,c=l,d=0,e=0,f=08 a=0,b=l,c=l,d=0,e=0,f=lThe problem is that the inputs change again before the logic values have time topropagate to the output.
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