Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 53
Текст из файла (страница 53)
keep the timing parameterizable.10.2 Without using a wand net, model a wired-AND configuration by employingopen-collector NAND gates and a pullup primitive.10.3 Model the following charge sharing circuit using appropriate trireg declarations:28210.410.510.610.710.810.9The Verilog Hardware Description LanguageWhat results from passing the following strength values through a resistive MOSgate:A) 0(00110000_00000000)B) X(00000011_00000001)C) 1(00000000_11111110)In the following two examples of combining strength values, one of them has anincorrect result, which one, and what should the result be?x(00000001_01111111) output 10(00100000_00000000) output 2x(00111111_01111111) result on net0(01100000_00000000) output 1x(01111111_00111111) output 20(01100000_00000000) result on netGiven the following about combining strength values for a wired-AND net type:0(01000000_00000000) output 11(00000000_01000000) output 20(01000000_00000000) result on wired-AND netWhat is the correct result for the following wired-AND combination?0(01100000_00000000) output 11(00000000_01100000) output 2Extend the miniSim description to include a cross-coupled NAND latch element.Extend the miniSim description to include a bufif1 gate element.
What outputvalues are generated when the control input is unknown and the data input is 0or 1?Add another net type that models a two input wired-AND element to theminiSim description. This element must allow the 0-strength component to winin situations of equal 0 and 1 strength (hint: the solution involves an alterationof the masking operation only).11ProjectsThe exercises at the end of the previous chapters have been short questions to helpyou think about the material in the chapter. This chapter contains two projects thateach encompass many aspects of the Verilog language. Each of these projects has beenused in Junior level university classes for electrical and computer engineering students.The projects are all open-ended; there is no one correct answer.
Instructors shouldrealize that the projects were aimed at a set of students with a certain course background that may not match the background of their current students. Further, theprojects were tailored to the specific material being presented in class at the time.Alter the projects by adding or deleting portions as needed.Some of these projects have supporting Verilog descriptions. These may beobtained from the e-mail reflector as described in the book’s Preface.11.1 Modeling Power DissipationHardware description languages are used to model various aspects of a system; performance and functionality being the two main ones.
With all the interest in buildinglow-power devices for handheld electronics, it is also important to model the powerThe Verilog Hardware Description Language284dissipation of a circuit during its operation. This problem asks you to write a Verilogdescription of several versions of a small system, and use these descriptions to compare and contrast the power dissipation of each.11.1.1 Modeling Power DissipationIn this assignment, we choose to model circuits at the gate level.
In CMOS circuits,power is only dissipated when a gate switches state. More specifically, when the gateoutput changes from a zero to a one, charge is drawn from the power supply to chargeup the output connection and drive the gates in the fanout list. In this model, we willassume that it takes no energy to hold a gate’s output value. Also, changing from anoutput 1 to 0 takes no energy. As a further tweak of the model, the energy needed toswitch from 0 to 1 is proportional to the gate’s fanout.We’ll build our circuit completely out of NAND gates.
But, Verilog’s built-in gateprimitives don’t count zero-to-one transitions — they only keep track of time andlogic value. Thus we need to build our own model of a NAND gate that keeps track ofthe number of zero-to-one transitions. This number will then be proportional topower dissipated in the circuit.11.1.2 What to doWe’ll build several versions of a circuit to implement the equation:Several versions? Well, let’s see. Assume that these are all 16-bit adds, and that eachadd has a combinational logic delay of time Here’s three versions to consider:The adds are organized like a balanced tree and the operations occur in a singleclock period of (essentially implementing a = ((b + c) + (d + e)).
i.e., b and c areadded together at the same time d and e are added together. Then the sums areadded producing a.There is an unbalanced tree of adds and a single clock period of (essentiallyimplementing a = (b + (c + (d + e))).And yet another version that takes two clock periods, each of time to implementthe balanced tree. That is, during the first clock period, b and c are added andstored in a register.
Also during that first clock period, d and e are added and putinto a separate register. During the second clock period, these two registers areadded.What you will do in this assignment is build these three circuits, run thousands ofinput vectors through them (hey, what’s a little computer time), and measure thepower dissipated by each.Projects28511.1.3 StepsA. Build a full adder module by instantiating 2-input NAND gates. At first, usegate primitives and give them all a unit gate delay (#1). Then build a 16-bitadder by instantiating full adder modules.
Use any form of carry logic you wish— ripple carry might be the easiest.B. Build the different circuits suggested above. Instantiate and connect the 16bit adder modules built in part A to do this. Ignore the carryout from the mostsignificant bit.
For each circuit, build a testbench module that will present inputvectors to your circuit. Use a random number generator (seeto generate 2000 different input sets. (An input set includes different numbers for b, c, d,and e.) Check a few to see if your circuits really do add the numbers correctly!C. Now that you have things working correctly, change the full adder module touse a new type of NAND gate called “myNAND” (or similar).
Write a behavioralmodel for myNAND that can be directly substituted for the original NANDS. Thatis, anytime any of the inputs change, the behavioral model should execute,determine if a zero-to-one output transition will occur, and then update a globalcounter indicating that the transition occurred. Of course, it should schedule itsoutput to change after a gate delay of time.
The global counter is a register in thetop module of the simulation which you will initialize to zero when simulationstarts. Anytime a zero-to-one transition occurs in any instantiated gate in thesystem, this counter will be updated. Use hierarchical naming to get access to it.You may want to consider what to do if the gate output changes from zero-toone and one-to-zero in zero time — there should be no expenditure of powernor change in logic output value.D. Change the delays of the myNAND module to be proportional to the numberof fanouts. Let’s say delay will just equal fanout.
Define a parameter in myNANDthat initializes the delay to 1. When you instantiate myNAND, override theparameter with a count of the gate’s fanout. (Be as accurate as you can.) Alsochange the model so that the global counter is incremented by the delay number. Thus a gate with large fanout will take more power every time it changesfrom zero to one, and it will also take more time to propagate the change.E. Compare the different circuits. Can you explain the differences in dissipationbased on the model we’re using?F. Extra, for fun.
Can you come up with a version that dissipates even lessenergy?286The Verilog Hardware Description Language11.2 A Floppy Disk Controller11.2.1 IntroductionIn this project, each two-person team will use Verilog to create a model of part of afloppy disk controller. A floppy disk controller takes a stream of data bits mingledwith a clock signal, decodes the stream to separate the clock and data, and computesthe Cyclic Redundancy Checksum (CRC) of the data to ensure that no errors haveoccurred. Once the data is found to be correct, it is placed in a FIFO, and from there itis placed into main memory via direct memory access (DMA).
Your Verilog model willtake the stream of data bits from the disk as input, and will negotiate with the memory bus as output.The parts of the controller are shown in Figure 11.1. For this project, you will buildVerilog models of the functions in the shaded area of Figure 11.1. Verilog models foreverything else are provided on the e-mail reflector. Each box in the figure representsa concurrent process.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
