Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 49
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Table 10.2 liststhe output from the simulation of this example.Module waveShReg initializes shiftin, phase1, and phase2 to zero, prints a headerline for the output table, and then sets up the monitoring of certain nets withininstance cct of module shreg. Note that the nets within instance cct are referencedSwitch Level Modeling255with the hierarchical naming convention (e.g. “cct.wbl”). The clockcct task is executed twice, evoking actions within the shift register. After two iterations of clockcct,the simulation is finished.Table 10.2 lists the output from the simulation.
Initially, the outputs are allunknown. After 100 time units the phase1 clock is set to one. This enables the passtransistor to conduct and the zero value at the input to be driven onto trireg net wa1after one gate delay. After one more gate delay, tri net wb1 becomes one because transistor b1 is cutoff and wb1 is connected to a pullup. No more gate action occurs untilthe phase1 clock goes to zero at time 200. At this point, we see the value on trireg netwa1 persisting even though there is no driver for that net. The phase2 clock thenbecomes 1 and the value on wb1 is transferred to wa2, driving transistor b2 and netwb2 to zero. Phase2 is lowered and phase1 is raised, shifting the bit to wa3, makingthe complement of the original input available at the output.
(Note that charge willremain on a net indefinitely unless there is a three-delay specifier placed on the net —the first being the delay to one, the second is the delay to zero, and the last is the delayto x.)References: Verilog gates D; strengths 10.2256The Verilog Hardware Description Language10.2 Switch Level ModelingSwitch level modeling allows for the strength of a driving gate and the size of thecapacitor storing charge on a trireg net to be modeled.
This capability provides formore accurate simulation of the electrical properties of the transistors than would alogic simulation.10.2.1 Strength ModelingConsider the description of a static RAM cell shown in Example 10.3 andFigure 10.2. Among other declarations, two NOT gates are instantiated, each with a“pull” drive strength; pull0 for the zero output strength, and pull1 for the one outputstrength. The pull drive strength is one of the possible strengths available in Verilog.It is weaker than the default strong drive which models a typical active drive gate output.In the example, the two NOT gates form a feedback loop that latches a valuedriven on w4 through the tranif1 gate. The tranif1 gate is a transfer gate that conductswhen its control input (address in this case) is one, and is nonconducting otherwise.The bufif1 gate is the read/write control for the circuit.
In read mode, the bufif1 control line (write) is zero and its output is high impedance. When the cell is addressed,the value in the latch is connected to the output buffer g5. In write mode when thecell is addressed, the bufif1 gate drives w4 through the tranif1 gate, possibly changingthe latch’s state.Example 10.3 also shows a Verilog module that will evoke the sram module andprint out the state of the nets in the circuit. The output is shown in Table 10.3 in atabular form. The method of modeling in this example shows us a static view of thecircuit; values are printed out after the “minor” gate changes have occurred.
(Note:The actual printout from simulating Example 10.3 has been edited for display inTable 10.3. Only the values printed are shown; the textual information such as“addr=” has been omitted. This is also true of Tables 10.6 and 10.8. In addition, thethree values for w134 are not shown in Table 10.3.)Switch Level Modeling257module sram(output dataOut,input address, dataIn, write);triw1, w3, w4, w43;bufif1tranif1not (pull0, pull1)bufendmoduleg1(w1, dataIn, write);g2(w4, w1, address);g3(w3, w4), g4(w4, w3);g5(dataOut, wl);module wave_sram; //waveform for testing the static RAM cell#(parameter d = 100);wiredataOut;regaddress, dataIn, write;sram cell (dataOut, address, dataIn, write);initial begin#d dis;#d address = 1;#d dataIn = 1;#d write = 1;#d write = 0;#d write = 'bx;#d address = 'bx;#d address = 1;#d write = 0;endtask dis;#d dis;#d dis;#d dis;#d dis;#d dis;#d dis;#d dis;#d dis;//display the circuit state"addr=%v d_In=%v write=%v d_out=%v",address, dataIn, write, dataOut," (134)=%b%b%b", cell.wl, cell.w3, cell.w4," w134=%v %v %v", cell.w1, cell.w3, cell.w4);endtaskendmoduleExample 10.3 A Static RAM CellThe Verilog Hardware Description Language258Note first that all values in the circuit start at x.
By time 500, the dataIn andaddress value are both 1. The tranif1 gate will transfer values in both directions. Thebufif1 gate, having an x on its control input, is driving its output to level H (meaning1 or z). Since this table only shows the Boolean values (as specified with the %b in thestatement) we see an x on the bufif1 output w1.At time 700, the write line has been one for 100 time units, driving w1 anddataOut to a one. Since the tranif1 gate is conducting, w1 and w4 are connected.
Atthis point, we have gate g4 (the NOT gate) and g1 (the bufif1 gate) both driving theseconnected lines. However, since g4 has been defined to have driving strength pull0and pull1 in the zero and one states respectively, its drive strength is not as strong asthe bufif gate which has the default strong drive strengths. In this case, the strongdrive overwhelms the pull drive and w4 follows w1, and w3 becomes the complement.w3 on the input to g4 then completes the changing of the ram cell value.At time 900, the write line is at zero, but the address line still selects the cell.
Thisis the read function of the sram module; the dataOut indicates the saved state.At time 1300, both address and write are x, and thus so is w1 and dataOut. However, the sram still holds its value. By time 1700, address and write indicate the readfunction and the value stored earlier is again conducted through the tranif1 gate to thedataOut.References:F.1; resistive gates 10.2.4Switch Level Modeling25910.2.2 Strength DefinitionsThe above example showed two of the levels of strength available in modeling switchlevel circuits; Table 10.4 is a complete list.
Again we can see that the strong drive ofthe bufif1 gate is stronger than the pull drive of the NOT gate.There are four driving strengths and three charge storage strengths. The drivingstrengths are associated with gate and continuous assignment outputs, and the chargestorage strengths are associated with the trireg net type.
The strengths may be associated with either a 1, 0, or x value. That is, a gate may drive a weak zero, a weak one, ora weak x. The declaration abbreviation should be used with a zero or one (e.g. pull0)when gate instances and strengths are declared. The printed abbreviation columnindicates how the strength is printed when the %v format is used (see later examples).Strengths associated with gate instances and assign statements are specified withinparentheses as shown in the examples and in the following formal syntax:gate instantiationn_input_gatetype [drive_strength] [delay2] n_input_gate_instance {,n_input_ gate_instance };|…continuous_assignassign [drive_strength] [delay3] list_of_net_assignments;The Verilog Hardware Description Language260drive_strength(strength0, strength1)|(strength1, strength0)(strength0, highly )||( strength1, highz0)|( highz1, strength0)( highz0, strength1)|strength0supply0 | strong0 | pull0 | weak0strength1supply1| strong1 | pull1 | weak1If the strengths are not given, then strong drives are assumed.
Only the gate typesshown in Table 10.5 support drive strength specifications:When a trireg net is declared, a charge storage strength is specified to model thesize of the capacitance exhibited by the net. However, charge stored in the net doesnot decay with time unless a three-delay specification is given.
The third delay parameter specifies the time until the stored charge decays to an x value. Trireg declarationsare a form of net specifications as shown in the formal syntax:net_declarationtrireg [charge_strength] [signed] [delay3] list_of_net_identifiers;|trireg [charge_strength] [signed] [delay3] list_of_net_decl_assignments;|trireg [charge_strength] [ vectored | scalared ] [signed] range [delay3]list_of_net_identifiers;|trireg[charge_strength] [ vectored | scalared ] [signed] range [delay3]list_of_net_dec1_assignments;charge strength(small) | (medium) | (large)References: net declarations 6.2.310.2.3 An Example Using StrengthsWe now look more closely at Example 10.3 and observe the gate strengths as they arecalculated and printed.
Thestatement:Switch Level Modeling261"address=%b dataIn=%b write=%b dataOut=%b",address, dataIn, write, dataOut,"(134)=%b%b%b", cell.w1, cell.w3, cell.w4," w134=%v %v %v", cell.w1, cell.w3, cell.w4);prints the w134 signals as binary numbers, using the %b control, and then asstrengths, using the %v control.
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