Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 46
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A positive edge on go is the signal to start a multiply. At that time,the inputs are multiplied together and product is scheduled to be updated on thefourth positive edge of clock. Since this is a non-blocking assignment, the calculatedproduct is stored internally in the event list and the always can then wait for the nextgo signal which will start another, possibly overlapping, multiply. In this situation, gomust be synchronous with respect to clock because we cannot have more than onemultiply started for each clock edge. However, we can have one multiply started eachclock period.
The example further illustrates that the event list can be used to storemultiple events for the same name and from the same assignment.module pipeMult(output reg [19:0] product,input[9:0] mPlier, mCand,inputgo, clock);always@(posedge go)product <= repeat (4) @(posedge clock) mPlier * mCand;endmoduleExample 8.12 A Pipelined MultiplierAn interesting contrast between gate level timing models and procedural timingmodels is illustrated here. If an update is generated for the output of an element usingthe Verilog gate level timing model, update events already scheduled in the event listfor that element will be removed and the new update will be scheduled. This is notthe case with elements using the procedural timing model.
As we have seen in thisexample, multiple update events for product are scheduled without changing any ofthe already scheduled update events.References: intra-assignment repeat 4.78.5 SummaryTiming models have been introduced as a means of separating simulation models intotwo broad classes characterized by how they advance simulation time. Algorithms fora simulator scheduler that handles these models was presented. Detailed limingissues, including non-determinism in the language and the contrast between blockingand non-blocking procedural assignments were covered.The Verilog Hardware Description Language2348.6 Exercises8.1 Below is a circuit and two Verilog models, one written as a structural model andthe other as a behavioral model.
Note that the models are not equivalent. Current logic levels are shown in the circuit. Assume there are no events in the eventlist except for those specified below.module sMux(output f,input a, b, select);module bMux(output reg f,inputa, b, select);nand#8(f, aSelect, bSelect),(aSelect, select, a),(bSelect, notSelect, b);not(notSelect, select);endmodulealways@select#8 f = (select) ? a : b ;endmoduleA. Simulate only module sMux and show all events that will eventually appearin the event list. The initial event in the event list is the update event “b = 0 attime 35”.
Separately simulate it with the initial update event as “select = 1 attime 50”.B. Simulate only module bMux and show all events that will eventually appearin the event list. The initial event in the event list is the update event “b = 0 attime 35”. Separately simulate it with the initial update event as “select = 1 attime 50”.C. As mentioned, the models are not equivalent. Briefly explain why the modelsare not equivalent. Change the bMux model to make it equivalent to sMux infunction and timing by rewriting the always statement.
Aspects you may or maynot want to consider: functionality only, input sensitivity, and/or timing withrespect to inertial delay. Explain your changes.D. As a function of time, what is the input sensitivity list of the always processstatement in bMux?Advanced Timing2358.2Fill in the following table by simulating module nbSchedule for 25 time units.Each line of the table represents a simulation cycle. You do not need to turn inthe event lists and how they change over tim. However, keeping the lists wouldprobably help you keep track of what you should put in the table.8.3Start executing the following description at time = 0 and stop at time = 40.module beenThere;module doneThat(input[15:0] que,reg[15:0] q;wireh;output regf,output reg [15:0] add);wire[15:0] addit;doneThat dT (q, h, addit);initial q = 20;always begin@ (posedge h);if (addit = = 1)q = q + 5;else q = q - 3;endendmodulealways#10 f = ~ f;initial beginf=0;add = 0;#14 add = que + 1;#14 add = 0;endendmoduleFill in the trace below (adding more lines), giving the time a register changes,the register name, and the new value assigned.
List these in time order.at time =8.4 Write and execute a test module for Example 8.12. The clock should have a 100ns. period. Several test vectors (numbers to multiply) should be loaded intomPlier and mCand and then go should be pulsed high for 10 ns. (Test module?See Chapter 1.)A. Show that your test module along with pipeMult produce correct answers.B.
Trace the update and evaluation events in the event list.The Verilog Hardware Description Language236module nbSchedule(output q2);wireregq1;c, a;xor(d, a, q1),(clk, 1'b1, c);// holy doodoo, Batman, a gated clock!s1(q1, d, clk),s2 (q2, q1, clk);dffinitial beginc=1;a = 0;#8 a = 1;endalways#20 c = ~c;endmodulemodule dff(output reg q,inputd, c);initial q = 0;always@(posedge c) q <= d;endmodule8.5 Here’s a skeleton of two modules (interleave and huh) that could have non-determinism problems due to interleaving with other behavioral processes.Where might a problem be encountered. Explain how to correct the problem.8.6 Remembering that there is some non-determinism built into the simulator,explain how different results can be obtained by simulating this circuit.
Suggesttwo different corrections to the description that remove the problem.Advanced Timingmodule interleave;reg[7:0]huhh ();237a;endmodulemodule huh;reg[7:0]b, c, q, r;always begina = b + c;q = a + r;endendmodulemodule ouch (select, muxOut, a, b);(inputselect,output reg muxOut,inputa, b);always begin@selectmuxOut = (a & select) | (b & notSelect);not(notSelect, select);endmodule8.7 Assuming that all registers are single-bit initially with the value x, contrast thetwo following situations.
At what times will the registers change?initial beginq = #15 1;r = #25 0;s = #13 1;endinitial beginq <= #15 1;r <= #25 0;s <= #13 1;endChange the pipeMult module in Example 8.12 so that it can only take new values every two clock periods. That is, the pipeline latency is still 4 clock periods,but the initiation rate is every two clock periods. Test the new module.8.9 Write a behavioral description that swaps the values in two registers withoutusing a temporary register.
The new values should appear #2 after the positiveedge. Complete the following module.8.8The Verilog Hardware Description Language238module swapIt(input doIt);reg[15:0] george, georgette;always@(posedge doIt)//do itendmodule8.10 Rewrite twoPhiLatch in Example 8.4 using a non-blocking assignment.8.11 Write a model for a simple component that requires the use of “<=” rather than“=” somewhere in the model. Example 8.12 was one such example; come upwith another.8.12 A student once asked if they could use blocking assignments rather than nonblocking assignments in their finite state machine descriptions. As it turns out,they could have but I would have pryed off their fingernails.
Keeping in mindthe differences between “may” and “can”, …A. Show an example where they can and it doesn’t matter. Explain why. Whatassumptions are required?B. Explain why they may not do this — briefly.9User-DefinedPrimitivesVerilog provides a set of 26 gate level primitives for modeling the actual logic implementation of a digital system. From these primitives, presented in Chapter 6, largerstructural models may be hierarchically described.
This chapter presents an advancedmethod for extending the set of gate level primitives to include user-defined combinational, and level- and edge-sensitive sequential circuits.There are several reasons for wanting to extend the set of gate level primitives.First, user-defined primitives are a very compact and efficient way of describing a possibly arbitrary block of logic. Secondly, it is possible to reduce the pessimism withrespect to the unknown x value in the simulator’s three valued logic, thus creatingmore realistic models for certain situations. Finally, simulation efficiency may begained through their use.
Note, however, that these may not be used to specifydesigns for logic synthesis.240The Verilog Hardware Description Language9.1 Combinational Primitives9.1.1 Basic Features of User-Defined PrimitivesAs shown in Example 9.1, user-definedprimitives are defined in a manner similarto a truth table enumeration of a logicfunction. Primitives are defined at the samelexical level as modules, i.e. primitives arenot defined within modules.
This exampledescribes a primitive for generating thecarry out of a single-bit full adder. carryOut is the output, and carryIn, aIn, andbIn are the inputs. A table is then specifiedshowing the value of the output for the various combinations of the inputs. A colonseparates the output on its right from theinputs on its left. The order of inputs in thetable description must correspond to theorder of inputs in the port list of the primitive definition statement. Reading from thefourth line of the table, if carryIn was 0,aIn was 1, and bIn was 1, then carryOutwould be 1.primitive carry(output carryOut,input carryIn, aIn, bIn);table0000100101101 001 011 101 11endtableendprimitive0;0;0;1;0;1;1;1;Example 9.1 A User-DefinedCombinational PrimitiveThere are a number of rules that must be considered:Primitives have multiple input ports, but exactly one output port.
They may nothave bidirectional inout ports.The output port must be the first port in the port list.All primitive ports are scalar. No vector ports are allowed.Only logic values of 1, 0, and x are allowed on input and output. The z value cannot be specified, although on input, it is treated as an x.The user-defined primitives act the same as other gate primitives and continuousassign statements.
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