Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 41
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the “+” and “-” in Verilog procedural statements)to functional modules. Given that a behavioral synthesis tool has decided to havetwo adders in the datapath, select which of the + operators in the description aregoing to be mapped into which of the functional modules.7.5 SummaryThis chapter has described the cycle-accurate style of specification in Verilog. Thisstyle is often used in high level simulation of systems and it is beginning to be used forbehavioral synthesis. Since synthesis technology is still young, the restrictions on thelanguage styles will evolve; the user manual for the tools must be consulted.8Advanced TimingThe previous chapters were based on a relatively straight-forward understanding ofhow the Verilog simulator schedules and executes events. This chapter develops amore detailed model of the simulator, including the processing of a number of themore subtle timing semantics of the language.
Topics include the simulator scheduling algorithm, non-deterministic aspects of the language, and non-blocking assignments.The material in this chapter is meant to explain conceptually how Verilog simulators are expected to work. However, the presentation may not match any particularimplementation. There are plenty of short-cuts, tricks, and go-fasts that are or couldbe implemented. Their mileage and software-engineering appropriateness may varyand are not the topic of the chapter.8.1 Verilog Timing ModelsA hardware description language is used to model both the function and timing ofdigital systems. The simulation of these models is organized around events.
An eventis a change in a value in the simulation model at a specific time. The semantics of thelanguage specify how an event causes other events to occur in time. Through thissequence of events, simulation models are executed, and simulation time is advanced.212The Verilog Hardware Description LanguageA timing model is a model of how simulation time is advanced — it is tied closely tothe semantics of the hardware description language. So far, we have seen two timingmodels used by the Verilog language. These timing models are illustrated by gate leveland behavioral level descriptions.A simulation model should not be confused with a timing model.
The first is a modelof digital hardware: e.g., an ALU or register file. The latter is a model of how time isadvanced by the simulator. In this section, we will discuss these timing models andhow the simulator advances time.Example 8.1 shows a simple NAND latch. By thesemantics of the language we know that when achange occurs on one of the gate inputs, that gatewill evaluate its inputs and determine if its outputis to change.
If it is, then after the specified gatedelay (#2), the output will change and be propagated. The gate instance is sensitive to its inputs —a change on any of these inputs will cause themodel of the gate instance to be executed.module nandLatch(output q, qBar,input set, reset);nand #2(q, qBar, set),(qBar, q, reset);endmoduleExample 8.1 A NAND LatchA simulation model has a sensitivity list — a listof inputs to the simulation model that, when a change occurs on one or more of them,will cause the model to be executed. The sensitivity list is a different view of a fanoutlist.
The fanout list is organized around the element producing a new value — it tellsus which elements need to be evaluated when an event occurs. The sensitivity list isorganized around the element receiving new values — it tells us which of the inputsare to cause the model to be executed when a change occurs.Example 8.1 illustrates the Verilog gate level timing model. When any input changesat any time, the gate instance will execute to evaluate its output, and create a newevent, possibly in the future, if the output changes. All inputs are always sensitive to achange; the change will cause the evaluation of the simulation model. The gate leveltiming model applies to all the gate primitives, user defined primitives, continuousassignment statements, and procedural continuous assignment statements.
A continuous assignment statement is sensitive to any change at any time on its right-handside. The change will cause the expression to be evaluated and assigned to the lefthand side, possibly at a future time.Another characteristic of the gate level timing model pertains to the scheduling ofnew events. Consider the situation where an event for a particular element exhibitingthe gate level timing model has previously been scheduled but has not occurred. If anew event is generated for the output of that element, the previously scheduled eventis cancelled and the new one is scheduled. Thus, if a pulse that is shorter than thepropagation time of a gate appears on the gate’s input, the output of the gate will notchange.
An inertial delay is the minimum time a set of inputs must be present for aAdvanced Timing213change in the output to be seen. Verilog gate models have inertial delays just greaterthan their propagation delay. That is, a pulse on a gate’s input will not be seen on theoutput unless its width is greater than the propagation delay of the gate. As we willsee, if the input pulse is equal to the propagation delay, it is indeterminate whether itaffects the output.
This is true for all elements exhibiting the gate level timing model.Now consider the behavioral model of a D flipflop shown in Example 8.2. The semantics of thelanguage tell us that the always statement willbegin executing and will wait for a positive edgeon the clock input. When a positive edge occurs,the model will delay five time units, set q equal tothe value on the d input at that time, and thenwait for the next positive edge on clock. In contrast to the gate level timing model, this exampleillustrates a different timing model.module DFF(output reg q,inputd, clock);always@ (posedge clock)#5 q = d;endmoduleExample 8.2 A BehavioralModel of a D Flip FlopThe always statement can be thought of as having two inputs (clock and d) andone output (q).
The always statement is not sensitive to any change at any time as thegate level timing model was. Rather, its sensitivities are control context dependent.For instance, during the time the always is delaying for five time units, another positive edge on the clock input will have no effect. Indeed that second positive edge willnot be seen by the simulation model since when the 5 time units are up, the modelwill then wait for the next clock edge. It will only be sensitive to positive clock edgesthat are greater than 5 time units apart. Thus the always statement is only sensitive toclock when execution of the model is stopped at the “@”. Further, the always statement is never sensitive to the d input — a change on d will not cause the always statement to do any processing.This example illustrates the Verilog procedural timing model which occurs in thebehavioral blocks contained in initial and always statements.
In general, the initial andalways statements are only sensitive to a subset of their inputs, and this sensitivitychanges over time with the execution of the model. Thus the sensitivities are dependent on what part of the behavioral model is currently being executed.Another characteristic of the procedural timing model pertains to how events arescheduled. Assume that an update event for a register has already been scheduled. Ifanother update event for the same register is scheduled, even for the same time, theprevious event is not cancelled. Thus there can be multiple events in the event list foran entity such as a register. If there are several update events for the same time, theorder of there execution is indeterminate.
This is in contrast to the gate level timingmodel where new update events for an output will cancel previously scheduled eventsfor that output.The Verilog Hardware Description Language214There is an overlap in the simulation models that can be built using the two Verilogtiming models. Indeed, in terms of input sensitivities, the procedural timing modelcan be used to model a super set of what a gate level timing model can. To see this,consider the behavioral NAND gate model shown in Example 8.3. This model uses theor construct with the control event (“@”) to mimic the input sensitivities of the gatelevel timing model.
If there is a change on in1, in2, or in3, the output will be evaluated. Thus, the procedural timing model can be used mimic the input sensitivities ofthe gate level timing model. However, as shown above, the procedural timing modelcan have other timing sensitivities, making it more flexible.module behavioralNand#(parameter delay = 5)(output reg out,inputin1, in2, in3);always@ (in1 or in2 or in3)#delay out = ~(in1 & in2 & in3);endmoduleExample 8.3 Overlap in Timing ModelsThere are several subtle differences between Example 8.3 and a three-input NANDgate instantiation. First, the procedural assignment makes the behavioral modelinsensitive to the inputs during the propagation delay of the gate.
Second, if theinputs of a gate level timing model change and there is already a new output scheduled for a future time, the previously scheduled update will be cancelled and a newevent will be scheduled.In summary, elements of a Verilog description follow either the gate level or procedural timing model. These timing models define two broad classes of elements in thelanguage, specifying how they are sensitive to changes on their inputs. Further, thesespecify two methods for how events are scheduled for future action.8.2 Basic Model of a SimulatorIn this section, we will develop a model for the inner workings of an event-drivensimulator — specifically how a simulator deals with the execution of simulation models that create events, and with the propagation of events that cause other simulationmodels to execute. Timing models are important to understand because each modelrequires different actions by the simulation algorithm.Advanced Timing2158.2.1 Gate Level SimulationConsider first the basic operation of a simulator as it simulates the gate level modelshown in Figure 8.1.
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