Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 40
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The initial block onlyspecifies the reset behavior.7.3 Mealy/Moore Machine SpecificationsExamples in the previous sections described the basics of modeling systems using thecycle-accurate approach. This section illustrates how these descriptions can be used asinput to behavioral synthesis tools.The examples illustrate several features in specification for behavioral synthesis.First, the placement of the clock events is arbitrary. They may be placed in conditionals, and there may be different numbers of them in different conditional control paths.204The Verilog Hardware Description LanguageThat is, each branch of an if-then-else need not have an equivalent number of states.Arbitrary placement of clock events in conditionals and loops allows the specificationof very complicated state transitions. For instance, you may traverse into severalnested loops before coming to a clock event.
The only restriction on their placement isthat a loop body must have at least one clock event specifier; it can be anywhere in theloop body.7.3.1 A Complex Control SpecificationExample 7.5 specifies an interpolating 3rd order FIR filter that samples its input (in)either every second or fourth clock period. Based on the sampled input, a new outputvalue y is calculated.
This value will appear on the output either two or four clockperiods in the future. The interpolated values for either one or three intermediateclock periods are calculated as the difference between the new value (out) and the previous value of y (yold). This is stored in delta and divided by two. If switch is equal tozero, delta is added to yold (also named out) to produce the single interpolated outputin the next state. If switch is equal to 1, delta is divided by two again and used to produce the interpolated outputs for the next three states.In the example, the final value of delta in state A depends on whether the thenpath of the if statement is taken.
That is, the control signals to the data path dependon state information (we’re in state A) as well as the system input switch. Thisrequires a Mealy machine implementation.Note that when writing to elements in the output set (in this case, out), a nonblocking assignment is used. This removes any problems with race conditions withany other assignments.
All of the other assignments are blocking, allowing the valuesassigned in one statement to be used in the next statements.7.3.2 Data and Control Path Trade-offsIn this section we consider two descriptions of an 8-point FIR filter specified forbehavioral synthesis using the cycle-accurate approach. In Example 7.6, arrayscoef_array and x_array are used to store the coefficients and previous inputs respectively. The filter reads a sample x every eight clock cycles and produces a result y everyeight cycles. Examples 7.6 and 7.7 produce the same simulation results but representdifferent implementations.Module firFilt in Example 7.6 takes two states to specify the FIR algorithm.
Thefirst state (A) determines initial values for the accumulator (acc), and the x_arrayvalue. In addition, the index is initialized to the starting position (start_pos). The second state (B) executes the body and end-condition check for the loop. Thus it has twonext states. The loop body will always generate new values for acc and index. If theloop is exited, based on the updated value of index, a new value of the output y andthe next starting position (start_pos) in the array are also generated. A disable state-Cycle-Accurate Specification205module synSwitchFilter(inputClock, reset, switch,input[7:0] in,output reg [7:0] out);reg[7:0]xl, x2, x3, y, yold, delta;initial forever @(negedge reset) begindisable main;out = 0;y = 1;x2 = 2;x3 = 3;endalways begin :mainwait (reset);@(posedge Clock)x1 = in;out <= y;yold = y;y = x1 + x2 + x3;delta = y - yold;delta = delta >> 1;if (switch = = 1) begindelta = delta >> 1;@(posedge Clock) out <= out + delta;@(posedge Clock) out <= out + delta;end@(posedge Clock) out <= out + delta;x3 = x2;x2 = x1;endendmoduleExample 7.5 Specification for Behavioral Synthesisment is used to specify a test-at-the-end loop.
When synthesized, the datapath and atwo-state controller will be generated.When using cycle-accurate specification, only one non-blocking assignment ismade to any member of the output set in a state. If two such assignments were madeto a register, its final value would be indeterminate.The Verilog Hardware Description Language206module firFilt(inputclock, reset,input[7:0] x,output reg [7:0] y);regregreg[7:0][7:0][7:0]coef_array [7:0];x_array [7:0];acc;reg[2:0]index, start_pos;//important: these roll over from 7 to 0initialforever @ (negedge reset) begindisable firmain;start_pos = 0;endalways begin: firmainwait (reset);@ (posedge clock);// State A;x_array[start_pos] = x;acc = x * coef_array[start_pos];index = start_pos + 1;begin :loop1forever begin@ (posedge clock); // State B;acc = acc + x_array[index] * coef_array[index];index = index + 1;if (index = = start_pos) disable loopl;endend // looply <= acc;start_pos = start_pos + 1;endendmoduleExample 7.6 Basic FIRThe state transition diagram of Example 7.6 is shown on the left-hand side ofFigure 7.4.
Along with the conditionals, only the names of the registers that are writ-Cycle-Accurate Specification207ten in the state are shown; the actual expression is not shown. The state transition diagram is quite straight-forward.Module firFiltMealy in Example 7.7 is a one-state specification of the FIR algorithm.
As is typical with Mealy machine implementations, actions are encoded on thedifferent next state arcs of the finite state machine. Here, the actions of firFilt aboveare so encoded. firFiltMealy shows three separate actions that can occur; all with thesame next state (which is the current state). The first action is the then part of the firstif statement. This corresponds to the initialization of the loop in firFilt.
The secondaction is the else part, which actually has two possible actions. The first action, whereloop1 is not disabled, updates acc and index and corresponds to the loop body of firfilt. The second action updates acc and index, but also updates y and start_pos. Thiscorresponds to exiting the loop in module firFilt. Interesting, when firFiltMealy issynthesized, there is no identifiable finite state machine.
All actions are conditionedby the comparison of registers index and start_pos; only datapath registers areclocked.The state transition diagram for Example 7.7 is shown on the right-hand side ofFigure 7.4. The same notation is used here; only the register name that are written areshown. In this case, the next state arc transited depends on the current value of indexand also the updated value of index. This updated value is shown here as index+1.The Verilog Hardware Description Language208module firFiltMealy(inputclock, reset,input[7:0] x,output reg [7:0] y);regregregreg[7:0][7:0][7:0][2:0]coef_array [7:0];x_array [7:0];acc;index, start_pos;initialforever @ (negedge reset) begindisable firmain;start_pos = 0;index = 0;endalways begin: firmainwait (reset);begin: looplforever begin@ (posedge clock);// State 1 — the only stateif (index = = start_pos) beginx_array[index] = x;acc = x * coef_array[index];index = index + 1;endelse beginacc = acc + x_array[index] * coef_array[index];index = index + 1;if (index == start_pos) disable loopl;endendendy <= acc;start_pos = start_pos + 1;index = start_pos;endendmoduleExample 7.7 Mealy FIRCycle-Accurate Specification209These examples illustrate the control a designer has in specifying complex controlstructures.7.4 Introduction to Behavioral SynthesisBehavioral synthesis tools aid in the design of register transfer level systems — finitestate machine with datapath systems.
As illustrated in Figure 7.5, a cycle-accuratedescription is used to specify the functionality of the system. From the cycle accuratenature of the description, timing relationships involving the inputs and outputs of thesystem are derived. The behavioral synthesis tool designs a datapath and finite statemachine implementing the functionality and meeting these timing relationships.
Thedesign is specified in terms of functional datapath modules such as ALUs, registerfiles, and multiplexor/bus drivers that are provided in a technology library file. Inaddition, the finite state machine for the system is specified. Downstream design toolsinclude logic synthesis to design the finite state machine and module generation todesign the datapath.Behavioral synthesis can be defined by its primary functions: scheduling, allocation, and mapping.Scheduling assigns operations to control states. Given that the input to a behavioralsynthesis system is a cycle-accurate specification, one might wonder what rolescheduling plays.
To behavioral synthesis, cycle-accurate specifications only constrain when input ports are read and when results are made available on an outputport. Internally, there is flexibility to schedule the operations that produce theresults as long as the result is available at the appropriate time.Allocation specifies how many of an object are used to implement the datapath.The cycle-accurate specification only tells us how to calculate the outputs from theinputs.
The behavioral synthesis tool selects the number of operators (i.e., shouldthere be one multiplier or two?), the number of registers, and the number of busesin a design. In conjunction with scheduling, allocation provides a wide range ofThe Verilog Hardware Description Language210trade-offs in implementation. That is, if two multipliers are available, then twomultiply operations could be done in one control state, making the implementation faster but larger.Mapping assigns operations (e.g.
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