Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 39

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The clock edge specifications are called clock events. Thus, we mightstate:always begin@ (posedge clock)q <= r + s;@ (posedge clock)qout <= q + qout;endHere, the clock events are the event control statements with the posedge specifier. Ofcourse, they could have been specified as negedge clocks as well.Consider how to read the above statements. The statement labelled State A aboveindicates the action that occurs in one state of the system. When the posedge of theclock is seen, q will be loaded with the sum of r and s. That is, even though q <= r + sis written on the text line after the event statement waiting for the edge, we knowfrom the simulation semantics of the language that q will be calculated based on val-The Verilog Hardware Description Language200ues of r and s existing just before the clock edge. q will be updated after all such righthand sides have been calculated.

Likewise, qout will be loaded at the second clockedge based on the value of q and qout just before this edge (this will be the q calculated in the previous state). From this specification, we infer that we have one clockperiod in which to calculate the sum of r, s, and qout. That is, in state A, the r and sinputs are sampled and summed to produce q. State B then accumulates that sum intoqout.The Verilog description is shown again in Figure 7.3, this time with a timing diagram and a state transition diagram. Note that the clock edge that transits the systemfrom state A to state B is the same one that loads the new value generated for q instate A.

Thus, the new value of q is generated by state A; it will not be available inregister q until the system is in state B.When modeling systems using the cycle-accurate approach, we are only samplingthe always block inputs on the edge of the clock at the end of the state. Thus, asshown in the figure, even though r and s were generated earlier in time (possibly at theprevious clock event), we only require that they be valid at the clock edge at the end ofthe state. After all, the specification is only accurate at the clock cycles (clock events);thus the name. Since all actions occur at the clock edge, assignments to members ofthe output set must be non-blocking.always begin@ (posedge clock)q <= r + s;@ (posedge clock)quot <= q + quot;endAn important notion in behavioral synthesis is that the timing relationshipsbetween the input and output sets specify the complete interface with the rest of thesystem.

That is, it is possible to synthesize alternate implementations of the behaviorthat have the same input/output timing relationships which may vary in the size ofthe implementation or its maximum clock frequency. Consider the Verilog fragmentin Example 7.3.Cycle-Accurate Specification(input[7:0]output reg [7:0][7:0]reg201i, j, k,f, h);g, q, r, s;always begin@ (posedge clock)f <= i + j;g=j*23;@ (posedge clock)h <= f + k;@ (posedge clock)f <= f* g;q = r * s;Example 7.3 Alternate Implementations of Cycle-Accurate SpecificationsAssume the output set is f and h, the input set is i, j, and k, and registers g, q, r, and sare part of the internal set.

Note that either of the multiplies in state C could havebeen executed in state B because the values being multiplied in each of the statementswere calculated before state B. Rescheduling one of these would be advantageousbecause state C has two multiplies scheduled in it. That means that the data path toimplement this Verilog fragment would have to have two separate multiply cells toexecute both multiplies in the same state. If we moved one of the multiplies to state B,then each of the states would only need one multiply in the data path — a savings inarea.

Behavioral synthesis tools are capable of recognizing the opportunities ofrescheduling operators into other states to make such savings.If q = r * s was moved into stateB, there would be no change in input/output functionality. However, if f <= f * g is moved, then f would appear one state too early. Thetiming relationships of the input and output sets would be changed, A behavioral synthesis tool knows to insert a temporary register to load this value in state B, and thentransfer the value to the output f in state C. It is possible that an extra register alreadyexists in the design.

For instance, if g is not accessed after state C before it is rewrittenin the next iteration of the always statement, the result of the multiply could be loadedinto register g and then transferred to register f in state C. The states B and C arerewritten below as Bnew and Cnew to illustrate this:The Verilog Hardware Description Language202@ (posedge clock)h <= f + k;g = f* g;@ (posedge clock)f <= g;q = r * s;One might observe that a designer can recognize these opportunities for optimization and could perform them. In fact, a designer could rewrite the descriptions as wehave to specify different schedulings of operations to control states.

However, abehavioral synthesis tool, given one of these specifications, can rapidly suggest alternate implementations that exhibit different trade-offs. The designer can select fromthe most appropriate. Not all behavioral synthesis tools can make all of these transformations. Your mileage may vary.References: always 3.1; thread of control 3.1; input set 2.3.17.2.3 Specifying the Reset FunctionThe example discussed above is expanded here in Example 7.4 to include a specification for the behavior of the circuit when it is reset. Module accumulate has ports forthe output (qout), ports for the inputs (r and s), as well as the special inputs for thesystem (clock and reset).The reset function for the always block is specified by an initial statement.

Here wehave specified an asynchronous reset that is asserted low. The initial block begins bywaiting for a negative edge on reset. When that occurs, the main block in the alwaysis disabled, qout is set to 0, and the next negative edge of reset is waited for. Thisaction causes the named begin-end block (main) to exit. When it exits, the alwaysrestarts it again and waits for reset to be TRUT (unasserted).

At some point, resetbecomes unasserted and the system will be in state A; at the first clock event, the system will transit from state A to state B. Note, though, that qout has been initializedto 0 through the reset, and the system will begin accumulating values from 0. Thefunctionality described is captured by the Verilog description and illustrated by thestate transition diagram in Example 7.4.There are a few points to note. If reset is unasserted, the behavior of the alwaysblock is that of the example in the previous section.

Reset could have been specified asasserted-high by waiting for the positive edge of reset in the initial block, and thenwaiting for ~reset in the always block. Finally, no action can be specified between the“wait(reset);” and the “@(posedge clock)”. Such an action can’t be part of state Bbecause it would have to be conditioned by the reset — an action not normallyallowed in finite state machine design. Any such action there would have to be implemented as another state executing when reset becomes unasserted and a clock eventCycle-Accurate Specification203module accumulate(output reg [11:0] qout,input[11:0] r, s,inputclock, reset);reg[11:0] q;initialforever @(negedge reset) begindisable main;qout <= 0;endalways begin: mainwait (reset);@ (posedge clock)q <= r + s;@ (posedge clock)qout <= q + qout;endendmoduleExample 7.4 Specifying the Reset Functionalitywould be needed so that it would clearly be part of a state.

Thus a clock event alwaysfollows the wait for an unasserted reset.Our full, cycle-accurate specification of a system now includes both the always andinitial blocks. Together these specify a thread of control and how that thread is resetinto a known state. When discussing the input and output sets of an always block atthis level of design, it is more accurate to consider both the always and initial blockstogether. Analyze only the always block to determine the sets.

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