Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 38
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The term cycleaccurate is used because the values in the system are specified to be valid only at thetime of the system’s state change — at a clock edge. This chapter presents the cycleaccurate method of specification, overviews behavioral synthesis, and illustrates howto specify systems for design using behavioral synthesis.7.1 Cycle-Accurate Behavioral Descriptions7.1.1 Specification ApproachScheduled behavior is specified using always blocks, and “@(posedge clock);” statements are used to break the specification into clock cycles or states. Example 7.1 illustrates a scheduled behavioral description of a simple calculation. The module hasports for registers x, y, and the clock. Register i, a loop counter, is only used inside themodule.The Verilog Hardware Description Language196Using the cycle-accurate style of description, an“@(posedge clock);” statement is followed by behavioral statements and thenby another “@(posedgeclock)” statement.
We’llcallthis“@(posedgeclock)” the clock event. Thestatements between thetwo clock events constitute a state. The clockevent statements need notappear in pairs; if there isonly one clock event statement in a loop body, thenthe loop executes in onestate and the next clockevent is, indeed, itself.module simpleTutorial(inputclock,output reg [7:0] x, y);reg[7:0] i;always begin@(posedge clock) x <= 0;i = 0;while (i <= 10) begin@(posedge clock);x <= x + y;i = i + 1;end@(posedge clock);if(x < 0)y <= 0;else x <= 0;endendmoduleIn example 7.1, considerstate C, the last clock eventExample 7.1 Description Using Scheduledand the statement that follows it as shown inFigure 7.1.
The statement that follows the clock event here is an if-else statement.Given that the always continuously loops, the next clock event is the one at the top ofthe always block, which starts state A. Thus, these statements show the specificationof one state. In that state, either y or x is assigned the value 0, depending on whetherx is less than 0. On the right of the figure the state corresponding to the description isshown.
Mealy notation is used (where outputs are a function of inputs and currentstate), indicating that if x is less than 0 then we’ll follow the top arc to state A andload register y with 0 (using a non-blocking assignment). The bottom arc shows theinverse condition when x is set to zero. In simulation, when the clock event before theif statement is being waited for, we are executing state C.@(posedge clock);if (x < 0)y <= 0;else x <= 0;Cycle-Accurate Specification197The full state transition diagram is shown in Figure 7.2. The state A initializes xand i to 0 and enters the loop. The state B is the loop body and state C is the if-else asdescribed above. The state B is of particular interest because it shows two possiblenext states.
The beginning of the state is the clock event statement in the loop body.However, the next clock event statement is either the one found by executing the loopbody and staying in the loop (i.e., the same statement), or the one found by executingthe loop body and exiting to the one just after the while statement. These account forthe two next states possible from state B.7.1.2 A Few NotesThere are a few interesting notes to be made about this example and the scheduledbehavior or cycle-accurate style of description.This style of description is used at the point in system design when we want tospecify the cycle-by-cycle behavior of the system but we are not too concerned withthe actual datapath for the design.
We have specified the simple calculation and whichstates the new values will be produced in. But, we haven’t specified any datapath for it;that is left for a later stage of the design process.The use of blocking (“=”) and non-blocking (“<=”) assignments was mixed in thisspecification. Non-blocking assignments were used for registers x and y which areused outside of the always block. This effectively synchronizes their loading to theclock edge specified. For registers used only in one always block, such as register i, thisis not necessary.
Remember that when you assign using non-blocking assignments,the value is not available by the register’s name until after the clock edge. i.e, it’s notavailable on the next line of the description! Further, only one unconditional nonblocking assignment can be made to any register in a state. However, you can useblocking assignments to calculate intermediate values and values only used inside thealways block. Of course, these are immediately available on the next line of thedescription. In this example, the i used in comparison at the end of the loop is the icalculated in the loop because we used a blocking assignment.198The Verilog Hardware Description Language7.2 Cycle-Accurate SpecificationThe basis for cycle-accurate specifications is the always statement, which is viewed asa specification of a thread of control: a process.
The resulting register-transfer levelimplementation of the always statement will include a data path to perform the processing specified in the always statement, and a description of a finite-state machineto evoke the register-transfer operations in the data path. A module may have multiple always statements in it. Each will be synthesized to a separate, although communicating, data path-finite state machine pairs.7.2.1 Inputs and Outputs of an Always BlockAlthough an always block is a behavioralmodule inOutExampleconstruct that does not have a formal specifi(input[7:0] r, s,inputclock,cation of ports, we can think of them as having ports.
Consider a module with a singleoutput reg [7:0] qout);always block and no other continuous assignreg[7:0] q;or module/gate instantiations as shown inExample 7.2. It is clear that the input andalways beginoutput ports of the module correspond to@ (posedge clock)the inputs and outputs of the always block.q <= r + s;That is, entities the always block needs as@ (posedge clock)inputs come from outside the module, andqout <= q + qout;entities the always block produces are madeavailable outside the module.
Of course,endendmodulethere may be some internal registers withvalues produced by the execution of thealways block and also used as input to it. Example 7.2 Illustration of alwaysBut, since such registers are not made avail- Block Input, Output, and InternalSetsable outside of the always block, they are notconsidered outputs.
And, since they are generated internally, their use is not considered an input.More formally, the internal register set of an always block is the set of all namedentities on the left-hand side of the procedural assignment statements in the alwaysblock that are only used internal to the always block. These include registers andmemories. In Example 7.2, register q is a member of the internal register set. Registerqout is not a member of the internal set because it is also used outside of the module.The input set of an always block includes all of the named entities on the righthand side of the procedural assignments in the always block and all of the namedentities in conditional expressions that are not members of the internal register set.That is, they are generated by a gate primitive, continuous assign, or another alwaysblock.
In Example 7.2, r and s are members of the input set.Cycle-Accurate Specification199The output set of an always statement is the set of all named entities on the lefthand side of the procedural assignment statements that are not members of the internal set. That is, these entities are used on the right-hand side of a continuous assign,are input to a gate primitive, or are in the input set of another always block. InExample 7.2, qout is a member of the output set. Even though qout is also used onthe right-hand side of this always block, it is the fact that it is used outside of thealways block that puts it in the output set.An always block used in cycle-accurate specification often has clock and resetinputs as well.
Indeed, Example 7.2 shows the use of input clock. For the sake of theabove definitions, we do not consider these to be inputs of the always block. Ratherwe will view them as special control inputs. This is similar to the practice in finitestate machine design where clock and reset are not considered part of the systemsinputs.
(To make our point, we intentionally left clock out of the input port list.)A module has many always blocks, gate instantiations, and continuous assign statements. Conceptually, we consider an always block as having ports made up of its inputset and output set. Although these ports are not formally listed, we view each alwaysblock as reading its inputs and producing its outputs and interacting with the rest of asystem through them.7.2.2 Input/Output Relationships of an Always BlockA cycle-accurate description is an always block that specifies the timing relationshipsbetween reading elements from the input set and producing values in the output set.The input/output relationships define the interface of the system to the outside world.These relationships are specified by inserting clock edge specifications in the procedural statements.
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