Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 33
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The value x is interpreted as“either 0 or 1 or in a state of change.” The z is a high-impedance condition. When thevalue z is present at the input of a gate or when it is encountered in an expression, theeffect is usually the same as an x value. It should be reiterated that even the registers inthe behavioral models store these four logic values on a bit-by-bit basis.Each of the primitive gates are defined in terms of these four logic values. Table 6.2shows the definition of an AND gate.
Note that a zero on the input of an AND willforce the output to a zero regardless of the other input — even if it is x or z.References: four-level gate definitions DLogic Level Modeling1636.2.3 NetsNets are a fundamental data type of the language, and are used to model an electricalconnection. Except for the trireg net which models a wire as a capacitor that storeselectrical charge, nets do not store values. Rather, they only transmit values that aredriven on them by structural elements such as gate outputs and assign statements, andregisters in a behavioral model.In Example 6.1 we see a net of type wire named x2 being declared. We could havedeclared it to have a delay with the following statementwire#3x2;meaning that any change of value driven on the wire from the first NAND gate instanceis delayed by 3 before it is seen at the wire’s terminations (which are the other NANDgate and the NOT gate). Further, the delay could include both rise and fall time specifications:wire#(3,5)x2;meaning that the transition to 1 has a 3 unit delay and the fall to 0 has a 5 unit delay.However, we also find many more wires declared implicitly in Example 6.1.
Forinstance, net x9 which is the output of the XNOR gate has not been declared in the ful1Adder module. If an identifier appears in the connection list of an instance of a gateprimitive, module, or on the left-hand side of a continuous assignment, it will implicitly be declared a net. If the net is connected to a module port, its default width will bethat of the port declaration.
Otherwise, it will be a scalar. By default, the type of animplicit declaration is wire. However, this may be overridden by the default_nettypetypeOfNet compiler directive where typeOfNet is any of the net types listed inTable 6.4 except the supply0 and supply1 types. Implicit net declaration can be turnedoff by declaring`default_nettype noneIn this case, any undefined identifier will be flagged as an error. One reason to turn offimplicit net declaration is to catch typing errors arising from letters and numbers thatlook alike, e.g., O,0,1,1.Thus, wire x2 need not have been declared separately here. It was only done so forillustration purposes.Example 6.2 illustrates the use of a different type of net, the wired-AND, or wand.The wired-AND performs the AND function on the net.
The only difference betweenthe AND gate and the wand is that the wand will pass a z on its input whereas an ANDgate will treat a z on its input as an x.The Verilog Hardware Description Language164module andOfComplements(inputa, b,output wand c,outputd);not (c, a);not (c, b);not (d, a);not (d,b);endmoduleExample 6.2 Wire AND ExampleHere we illustrate the differences between the normal wire and wand net types, d isdeclared to be a wire net, and c is declared to be a wand net. c is driven by two different NOT gates as is d. A net declared wand will implement the wired-AND function.The output c will be zero if any one of the inputs to the wand net is zero (meaningthat one of the inputs, a or b, was one).
The output c will be one if both of the inputsa and b are zero.On the other hand, d is a wire net driven by two gates. Its value will be unknown(x) unless both gates drive it to the same value. Essentially the wand allows for severaldrivers on the net and will implement the wired-AND function between the drivers,while the wire net will show an unknown (x) when different values are driven on it.Table 6.3 shows the outputs for all possible inputs to Example 6.2 (The sixteen rowsof the truth table are folded into two columns of eight rows).Logic Level Modeling165The general form of the net declaration is:net_declarationnet_type [ vectored | scalared ] [signed] range [delay3]list_of_net_identifiers;| net_type [signed] [delay3] list_of_net_identifiers;| net_type [drive strength] [ vectored | scalared ] [signed] range [delay3]list_of_net_decl_assignments;|net_type [drive strength] [signed] [delay3] list_of_net_decl_assignments;| trireg [charge_strength] [ vectored | scalared ] [signed] range [delay3]list_of_net_identifiers;net_typewire | tri | tril | supply0 | wand | triand | tri0 | supply1 | wor | triorlist_of_net_identifiersnet_identifier [dimension {dimension}] {, net_identifier [dimension {dimension}] }list_of_net_assignmentsnet_decl_assignment {, net_decl_assignment}net_decl_assignmentnet_identifier = expressionrange[ msb_constant_expression: 1sb _constant_expression ]We’ll concentrate on the first net declaration in this section.
net_type is one of thetypes (such as wire and wand) listed in Table 6.4, signed indicates if the wire’s valuesare to be considered signed when entering into expressions, range is the specificationof bit width (default is one bit), delay provides the option for the net to have its owndelay (default is 0), and list_of_net_identifiers is a comma-separated list of nets thatwill all have the given range and delay properties. When a delay is specified on a net,the new value from any entity driving the net will be delayed by the specified timebefore it is propagated to any entities connected to the net.The range of nets can optionally be declared as vectored or scalared. Scalered is thedefault case and indicates that the individual bits of a vector (i.e. a multibit net) mightbe accessed using bit- and part-selects. This allows individual bits and parts of a net tobe driven by the outputs of gates, primitives, and modules, or to be on the left-handside of a continuous assign.
When specified as vectored, the items are representedinternally as a single unit for efficiency. In this case, for instance, gate outputs cannotdrive a bus specified as vectored.166The Verilog Hardware Description LanguageReferences: trireg 10.1; charge storage properties 10.2.2; delay 6.5; continuous assign to nets 6.3.2;primitives 9; bit- and part-selects E.1; scope of identifiers 3.66.2.4 A Logic Level ExampleAs an example of logic level modeling, this section presents a system implementing aHamming encoding and decoding function.
Hamming encoding is used when thereis a possibility of noise entering a system and data being corrupted. For instance, datain a memory might be stored in an encoded form. The example presented here willencode eight bits of data, pass the encoded data through a noisy channel, and thenregenerate the original data, correcting a single bit error if necessary. Detailed derivation and presentation of the technique can be found in most introductory logic designtexts.The error detection and correction is implemented by adding extra bits to the message to be encoded. The basic encoding is shown in Figure 6.2. Here we see eightoriginal bits (Dx) on the left being encoded into twelve bits on the right. The originaldata bits are interleaved with four Hamming bits (Hx) as shown in the center column.The four bits are determined by XORing certain of the original bits.
The interleavedordering of the bits is important as the final decoding of the bits will indicate which ofthe bits (including the Hamming bits) is incorrect by specifying its bit position. Thebit numbering of the encoded data is shown on the right.The whole picture of our example, which includes this encoding function, is shownin Figure 6.3. We will have one module, testHam, which instantiates all of the othermodules and provides test vectors to it. Submodules to testHam include hamEncode,which implements the function in Figure 6.2, and hamDecode, which itself has several submodules.
There is also an assign statement shown in gray in the center of theLogic Level Modeling167figure that will insert a single error into the data after it is encoded. The hamDecodemodule regenerates the original eight-bit message by correcting any single bit errors.A simulation trace of the whole system is presented in Figure 6.4, illustrating the values passed between the major subentities of testHam (namely, original, encoded,messedUp, and regenerated).The Hamming code example is shown in Example 6.3.
Module hamEncode generates the twelve-bit encoding (valueOut) of vIn. The encoding is implemented withfour instantiated XOR gates implementing the encoding functions shown inFigure 6.2. The outputs of these gates are connected to wires (h1, h2, h4, and h8) andthe wires are concatenated together with the data bits in the assign statement.
Concatenation is indicated by the “{}” construct. The comma separated list of wires andpart-selects of wires is combined into the output valueOut. Note that the order inwhich the values are concatenated matches that given in Figure 6.2. It is also interesting to note that the module is completely structural in nature; there are no proceduralstatements or registers.The Verilog Hardware Description Language168Module hamDecode takes the 12-bit input vIn and produces the 8-bit output valueOut. Internally, hamDecode needs to determine which of the bits (if any) is incorrect,and then correct it. The four XOR gates producing outputs on c1, c2, c4, and c8 indicate if a bit is incorrect. Consider the c’s to be the separate bits of a vector; c8 hasplace-value 8, and so on.
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