Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 30
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An output port specifies the internal name for a vector or scalar whichis driven by an internal entity and is available external to the module. An inout port144The Verilog Hardware Description Languagespecifies the internal name for a vector or scalar that can be driven either by an internal or external entity.It is useful to recap some of the do’s and don’t’s in their specification.
First, an inputor inout port cannot be declared to be of type register. Either of these port types maybe read into a register using a procedural assignment statement, used on the righthand side of a continuous assignment, or used as input to instantiated modules orgates. An inout port may only be driven through a gate with high impedance capabilities such as a bufif0 gate.Secondly, each port connection is a conmodule binaryToESegtinuous assignment of source to sink where(input A, B, C, D,one connected item is the signal source andoutput eSeg);the other is a signal sink.
The output portsof a module are implicitly connected to signand #1nal source entities such as nets, registers,g1 (p1, C, ~D),gate outputs, instantiated module outputs,g2 (p2, A, B),and the left-hand side of continuousg3 (p3, ~B, ~D),assignments internal to the module. Inputg4 (p4, A, C),ports are connected to gate inputs, instantig5 (eSeg, p1, p2, p3, p4);ated module inputs, and the right-handendmoduleside of continuous and procedural assignments.
Inout ports of a module are connected internally to gate outputs or inputs. Externally, only nets may be connected toa module’s outputs.Finally, a module’s ports are normally connected at the instantiation site in theorder in which they are defined. However, we may connect to a module’s ports bynaming the port and giving its connection. Given the definition of binaryToESeg,reprinted here from Example 1.3, we can instantiate it into another module and connect its ports by name as shown below. Example 1.11 instantiated this module usingthe statement:binaryToESeg disp m1 (eSeg, w3, w2, w1, w0);where eSeg, w3, w2, w1, and w0 were all declared as wires.
(The module instancename m1 has been added here to help the discussion.) Alternately, the ports couldhave been specified by listing their connections as shown below:binaryToESeg disp m1 (.eSeg(eSeg), .A(w3), .B(w2), .C(w1), .D(w0));In this statement, we have specified that port eSeg of instance m1 of module binaryToESeg will be connected to wire eSeg, port A to wire w3, port B to wire w2, port Cto wire w1, and port D to wire w0. The period (“.”) introduces the port name asdefined in the module being instantiated. Given that both names are specifiedtogether, the connections may be listed in any order. If a port is to be left uncon-Module Hierarchy145nected, no value is specified in the parentheses — thus .D() would indicate that noconnection is to be made to port D of instance m1 of module binaryToESeg.At this point we can formally specify the syntax needed to instantiate modules andconnect their ports.
Note that the following syntax specification includes both meansof listing the module connections: ordered-port and named-port specifications.module instantiationmodule _identifier [ parameter_value_assignment ] module_instance {,module_instance };parameter_value_assignment# (expression {, expression } )module_instancename_of_instance ([list_of_module_connections])name_of_instancemodule_instance_identifier [ range ]list_of_module_connectionsordered_port_connection {, ordered_port_connection }named_port_connection {, named_port_connection }ordered_port_connection[ expression ]named_port_connectionport_identifier ([ expression ])146The Verilog Hardware Description Language5.2 ParametersParameters allow us to enter definenames for values and expressions thatwill be used in a module’s description.
Some, for instance alocalparam, allow for the specification of a constant, possibly through acompile-time expression. Others(parameter) allow us to define ageneric module that can be parameterized for use in different situations.Not only does this allow us to reusethe same module definition in moresituations, but it allows us to definegeneric information about the module that can be overridden when themodule is instantiated.module xor8(output [1:8]input [1:8]xorxout,xin1, xin2);(xout[8], xinl [8], xin2[8]),(xout[7], xinl [7], xin2[7]),(xout[6], xinl [6], xin2[6]),(xout[5], xinl [5], xin2[5]),(xout[4], xinl [4], xin2[4]),(xout[3], xinl [3], xin2[3]),(xout[2], xinl [2], xin2[2]),(xout[l], xinl [l], xin2[l]);endmoduleExample 5.1 An 8-Bit Exclusive OrExample 5.1 presents an 8-bit XOR module that instantiates eight XOR primitivesand wires them to the external ports.
The ports are 8-bit scalars; bit-selects are used toconnect each primitive. In this section we develop a parameterized version of thismodule.First, we replace the eight XOR gateinstantiations with a single assignstatement as shown in Example 5.2,making this module more generallyuseful with the parameter specification.Here we specify two parameters, thewidth of the module (4) and its delay(10).
Parameter specification is part ofmodule definition as seen in the following syntax specification:module xorx# (parameter width = 4,delay = 10)(output [l:width] xout,input [1:width] xinl, xin2);assign #(delay) xout = xin1 ^ xin2;endmoduleExample 5.2 A Parameterized Modulemodule_declarationmodule_keyword module_identifier [ module_parameter_port_list][list_of_ports];{ module_item }endmodule| module_keyword module_identifier [ module_parameter_port_list][list_of_ports_declarations];{ non_port_module_item }endmoduleModule Hierarchy147module_parameter_port_list# (parameter_declaration { , parameter_declaration})parameter_declarationparameter [ signed ] [ range ] list_of_param_assignments;parameter integer list_of_param_assignments;parameter real list_of_param_assignments;parameter realtime list_of_param_assignments;parameter time list_of_param_assignments;The module_parameter_port_list can be specified right after the module keywordand name; the types of parameters that can be specified include signed, sized (with arange) parameters, as well as parameter types integer, real, realtime, and time.Local parameters have a similar declaration style except that the localparam keyword is used instead of parameter.local_parameter_declarationlocalparam [ signed ] [ range ] list_of_param_assignments;localparam integer list_of_param_assignments;localparam real list_of_param_assignments;localparam realtime list_of_param_assignments;localparam time list_of_param_assignments;These cannot be directly overridden and thus are typically used for defining constantswithin a module.
However, since a local parameter assignment expression can containa parameter (which can be overridden), it can be indirectly overridden.When module xorx is instantiated,module overriddenParametersthe values specified in the parameter(output [3:0] a1, a2);declaration are used. This is a genericinstantiation of the module. However,reg[3:0]b1, c1, b2, c2;an instantiation of this module mayoverride these parameters as illustratedxorx#(4, 0) a(a1, b1, c1),in Example 5.3. The “#(4, 0)” specifiesb(a2, b2, c2);that the value of the first parameterendmodule(width) is 8 for this instantiation, andthe value of the second (delay) is 0.
If theExample 5.3 Overriding GenericParameters“#(4, 0)” was omitted, then the valuesspecified in the module definition wouldbe used instead. That is, we are able to override the parameter values on a per-module-instance basis.The order of the overriding values follows the order of the parameter specificationin the module’s definition.
However, the parameters can also be explicitly overriddenby naming the parameter at the instantiation site. Thus:The Verilog Hardware Description Language148xorx#(.width(4), .delay(0)a(a1, b1, c1),b(a2, b2, c2);would have result as the instantiation of xorx in Example 5.3. With the explicitapproach, the parameters can be listed in any order.
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