Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 32
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Write thestructural Verilog description that will be correct in functionality and timing.6Logic LevelModelingTo this point, we have concentrated mostly on behavioral modeling of a digital system. Behavioral models are more concerned with describing the abstract functionalityof a module, regardless of its actual implementation. Logic level modeling is used tomodel the logical structure of a module, specifying its ports, submodules, logical function, and interconnections in a way that directly corresponds to its implementation.This chapter presents the Verilog constructs that allow us to describe the logical function and structure of a system.6.1 IntroductionThere are several approaches to the logic level modeling of a digital system.
Each ofthese approaches represents a sublevel of logic level modeling, and emphasizes different features of a module.A gate level model of a circuit describes the circuit in terms of interconnections oflogic primitives such as AND, OR, and XOR. Modeling at this level allows the designerto describe the actual logic implementation of a design in terms of elements found ina technology library or databook and thus be able to accurately analyze the design forsuch features as its timing and functional correctness. Since gate level modeling is so158The Verilog Hardware Description Languagepervasive, the Verilog language provides gate level primitives for the standard logicfunctions.A more abstract means of describing the combinational logic of a design is provided by the continuous assignment statement.
This approach allows for logic functionsto be specified in a form similar to Boolean algebra. The continuous assignment statement typically describes the behavior of a combinational logic module, and not itsimplementation.Finally, the Verilog language allows us to describe a circuit at the transistor switchlevel. At this level, the language provides abstractions of the underlying EOS andCEOS transistors, giving the designer access to some of the electrical characteristics ofthe logic implementation.To help in reading and writing models at these levels, it is useful to understand howthe simulator executes them.
The basic data type in this style of modeling is the netwhich is driven by gate and continuous assign outputs. These nets then are inputs toother gates and continuous assigns, as well as to the right-hand side of proceduralassignment statements. Anytime the input to a gate or continuous assign statementchanges, its output is evaluated and any change to the output is propagated, possiblywith a delay, via its output net to other inputs. We call this method of updating outputs when any input changes the Verilog gate level timing model; this is discussed further in Chapter 8.In contrast, procedural assignment statements found in behavioral modeling onlyexecute when control is passed to them.
Thus just because a net on the right-handside of a procedural assignment statement changes doesn’t mean that the statementwill execute. Rather, that input would have to have been to an event (“@”) or waitstatement which when triggered will cause the procedural statements in the behavioral model to execute.The language provides different methods for the designer to describe a system, thusallowing the description to be at the level of detail appropriate to the designer’s needs.These different methods of describing the logic level function and structure of a system are presented in this and the next two chapters.References: contrast to procedural assignment 3.1; gate level timing model 8.16.2 Logic Gates and NetsWe start with modeling a system at the logic gate level.
Verilog provides a set of 26gate level primitives that have been predefined in the language. From these primitives,we build larger functional modules by interconnecting the gates with nets and enclos-Logic Level Modeling159ing them into modules. When describing a circuit at the gate level, we try to maintaina close (some might say strict) correspondence to the actual gate level implementation.6.2.1 Modeling Using Primitive Logic GatesExample 6.1 shows a structural model of afull adder using some of Verilog’s gate levelprimitives.
This example was developed froma databook description of a CEOS one-bit fulladder. Three single bit inputs and two singlebit outputs provide connection to the outsideworld. Internal to the module description, welist the eleven primitive logic moduleinstances that comprise the adder. Figure 6.1shows a diagram of the adder with the internal connections labelled for ease of comparison.
As a partial explanation, we see thatthere are two NAND gates, one with output x2(note that the first parameter of a gate levelprimitive is its output) and inputs aIn andbIn, and the other with output cOut andinputs x2 and x8.module fullAdder(output cOut, sum,input aIn, bIn, cIn);wirex2;nand(x2, aIn, bIn),(cOut,x2,x8);(x9, x5, x6);(x5, x1, x3),(xl, aIn, bIn);(x8, xl, x7);(sum, x9),(x3,x2),(x6, x4),(x4,cIn),(x7, x6);xnornorornotendmoduleExample 6.1 A One-Bit Full Adder160The Verilog Hardware Description LanguageThe general syntax for instantiating a gate is given by:gate instantiationn_input_gatetype [drive_strength] [delay2] n_input_gate_instance {,n_input_ gate_instance };n_input_gatetypeand | nand | or | nor | xor | xnorn_input_gate_instance[name_of_gate_instance](output_terminal,input_terminal {,input_terminal})name_of_gate_instancegate_Instance_identifier [range]input_terminalexpressionoutput_terminalnet_lvaluewhere the n_input_gatetype specifies one of the gate level primitives listed above, theoptional drive_strength specifies the electrical characteristics of the gate’s output, theoptional delay specifies the simulation gate delay to be used with this instance, and thelist of gate instances is a comma-separated list specifying the terminals of each gateinstance and, optionally, names of each instance.
The default strengths are strong0and strong1. The default delay is 0. Further discussion of strengths is given inChapter 10 and a further discussion of delay modeling is in sections 6.5 and 6.6.Note that the above formal specification does not cover the NOT gate shown inExample 6.1.
NOT and BUF gates may have any number of outputs (listed first) butonly one input, as described formally below:gate instantiationn_output_gatetype [drive_strength] [delay2] n_output_gate_instance {,n_output_gate_instance };n_output_gate_instance[name_of_gate_instance]( output_terminal {, output_terminal},input_terminal)n_output _gatetypebuf | notLogic Level Modeling161In Example 6.1, we have not named any of the gate instances. However, we couldname the NAND gates by changing the statement to:nandJohn (x2, aIn, bIn),Holland (cOut,x2,x8);Or, we could have specified a strong0 and strong1 drive, as well as a 3 unit gate delayfor each of John and Holland.nand (strong0, strong1) #3John (x2, aIn, bIn),Holland (cOut, x2, x8);The drive strength and delay specifications qualify the gate instantiation(s).
Whenone (or both) of these qualifiers is given, then it applies to all of the defined instancesin the comma-separated list. To change one or both of these qualifiers, the gateinstantiation list must be ended (with a “;”) and restarted.A complete list of predefined gate level primitives is given in Table 6.1. For the restof the chapter, we will concern ourselves with the primitives in the first three columns.They represent logic abstractions of the transistors from which they are made.
Theother entries in the last three columns allow for modeling at the transistor switchlevel. These switch level elements will be discussed in Chapter 10.The gate primitives in the first column of Table 6.1 implement the standard logicfunctions listed. In the second column, the buf gate is a non-inverting buffer, and thenot gate is an inverter.
In the third column, the bufif and notif gates provide the bufand not function with a tristate enable input. A bufif0 drives its output if the enable is0 and drives a high impedance if it is 1. The 4-level truth tables (using 0,1, x, and z)for Verilog gates may be found in Appendix D.For the gate level primitives in the first column, the first identifier in the gateinstantiation is the single output or bidirectional port and all the other identifiers areThe Verilog Hardware Description Language162the inputs.
Any number of inputs may be listed. Buf and not gates may have anynumber of outputs; the single input is listed last.Although the drive strength will be discussed further in Chapter 10, it is useful topoint out that a strength may only be specified for the gates listed in the first threecolumns.References: Verilog primitive gates D; four-level logic 6.2.2; strengths 10.2; delay specification 6.5; switchlevel gates 10; user-defined primitives 96.2.2 Four-Level Logic ValuesThe outputs of gates drive nets that connect to other gates and modules. The valuesthat a gate may drive onto a net comes from the set:01xzrepresents a logic zero, or FALSE conditionrepresents a logic one, or TRUE conditionrepresents an unknown logic value (any of 0,1, or in a state of change)represents a high-impedance conditionThe values 0 and 1 are logical complements of each other.
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