Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 35
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Instead of using Boolean algebra to describe amultiplexor, Example 6.5 used procedural statements. The use of procedural statements in a function called from an assign merely gives us another method of describing the combinational behavior. Modeling in this way does not imply the use of aThe Verilog Hardware Description Language174sequential state machine for implementation and should not be used when sequentialactivity is to be modeled.References: functions 3.5.26.3.2 Net and Continuous Assign DeclarationsContinuous assign statements specify a value to be driven onto a net asshown in Example 6.6.module modXor(output [7:0]input [7:0]AXorB,a, b);Here we have defined a vector wireassign #5 AXorB = a ^ b;with eight bits and an eight-bitendmoduleexclusive-or of inputs a and b whichdrive them.
The delay specifies the Example 6.6 Combined Net and Continuousdelay involved in the exclusive-or,Assignmentnot in the wire drivers.If we had declared the wire and exclusive-or separately aswireassign[7:0]#5AXorB;AXorB = a ^ b;we could have assigned a separate delay of 10 to the wire drivers by substituting thestatement:wire[7:0]#10 AXorB;When a delay is given in a net declaration as shown, the delay is added to anydriver that drives the net. For example,consider the module in Example 6.7.
Wehave defined a wand net with delay of 10and two assign statements that both drivethe net. One assign statement has delay 5and the other has delay 3. When input achanges, there will be a delay of fifteenbefore its change is reflected at the inputsthat c connects to.
When input bchanges, there will be a delay of thirteen.module wandOfAssigns(input a, b,output c);wand#10c;assign #5 c = ~a;assign #3 c = ~b;endmoduleExample 6.7 Net and ContinuousAssignment DelaysThe combined use of a net specification and continuous assign is formally specifiedwith the following descriptions of a net_declaration:net_declaration| net_type [drive strength] [ vectored | scalared ] [signed] range [delay3]Logic Level Modeling175list_of_net_decl_assignments;net_type [drive strength] [signed] [delay3] list_of_net_decl_assignments;list_of_net_decl_assignmentsnet_decl_assigmnent {, net_decl_assignment}net_decl_assignmentnet_identifier = expressionThe difference compared to the first entry is that strengths can be specified, and thatthere is a list of assignments associated with a strength-range-delay combination.Continuous assignment statements may also be used to drive an inout port.Example 6.8 shows an example of a buffer-driver.module bufferDriver(inout busLine,output bufferedVal,input bufInput, busEnable);assignbufferedVal = busLine,busLine = (busEnable) ? bufInput: 1'bz;endmoduleExample 6.8 Continuous Assignment to an InoutHere we see busEnable being used to select between bufInput driving the busLineand a high impedance driving the line.
However, no matter what the state of busEnable, bufferedVal always follows the value of busLine. Thus busLine may be driven inan external module when busEnable is zero and bufferedVal will show its value.176A typical use of tristate driversis in a memory module designedto attach to a processor bus.Example 6.9 illustrates a 64Kbyte memory. The dataBus portis defined to be an inout, allowing it be driven in the module’sassign statement and also be usedas the source when writingmemory. Writing the memory isa synchronous activity controlled by the positive edge of theclock. A new value is read fromthe memory when read enable(re) first becomes asserted (i.e.,the negative edge), or when thereis a change on the address lines(addrBus). The value read isstored in temporary register outwhich drives the dataBus whenre is asserted.
If re is unasserted,dataBus is tristated.The Verilog Hardware Description Languagemodule Memory_64Kx8(inout [7:0] dataBus,input [15:0] addrBus,inputwe, re, clock);regreg[7:0][7:0]out;Mem [65535:0];assign dataBus = (~re)? out: 16'bz;always @(negedge re or addrBus)out = Mem[addrBus];always @(posedge clock)if (we = = 0)Mem[addrBus] <= dataBus;endmoduleExample 6.9 Memory Module With TristateDriversReferences: nets, vectored/scalared 6.2.36.4 A Mixed Behavioral/Structural ExampleExample 4.8 presented an example of a synchronous bus.
In this section we will alterthe description by modeling the bus lines using wires rather than registers, andparameterizing the modules to make them more generically useful. The new model isshown in Example 6.10. The bus protocol and the organization of the Verilogdescription are the same as in the earlier example. The reader is referred to the earlierpresentation in section 4.4 as background for this section.Again we have a bus master process communicating with a bus slave process. Incontrast to the previous example, the communication in Example 6.10 is carried outover wires defined in the sbus module. Here we see wires rw, addr, and data being theonly means of communication between the instantiated master and slave modules.The rw and addr lines are driven only by the bus master. However, the data linesmust be driven during a write cycle by the master, and during a read cycle by theslave. Thus we need to develop a means of synchronizing the driving of the data lines.Of course, the rw line produced by the master is the global indicator of whether a busread or write is in progress.
Both the master and slave modules include a registerLogic Level Modeling177called enable which is used internally to enable the bus drivers at the appropriatetimes.Module busDriver is defined in a manner similar to the bus driver in Example 6.8.The main difference being that the module does not also act as a bus receiver. Themodule is parameterizable to the bus size, and will drive the bus with valueToGo ifdriveEnable is TRUE. Otherwise it drives a z. This module is instantiated into boththe master and slave modules.In the slave module, the enable register has been added to control the bus driver.Enable is set to 0 during initialization which causes the bus line to be at z.
Enable isthen set to 1 during the second clock cycle of the read cycle. This is the time when thevalue being read is driven on the bus by the slave. In the master module a separateenable has been added to control the bus driver. Again enable is set to 0 during initialization. The master sets enable to 1 during the write cycle as it is during this timethat the master drives the data bus.The sbus module has been set up so that it can be instantiated with parameters ofclock period, address and data bus size, and memory size.
Thus it can be used in anumber of modeling situations.`define READ 0`define WRITE 1module sbus;parameterTclock = 20,Asize = 5,Dsize = 16,Msize = 32;reg clock;wirewirewirerw;[Asize-1:0] addr;[Dsize-l:0] data;master #(Asize, Dsize)slave #(Asize, Dsize, Msize)ml (rw, addr, data, clock);s1 (rw, addr, data, clock);initialbeginclock = 0;("rw=%d, data=%d, addr=%d at time %d",rw, data, addr,The Verilog Hardware Description Language178endalways#Tclock clock = !clock;endmodulemodule busDriver#(parameter Bsize = 16)(inout [Bsize-1:0] busLine,input [Bsize-1:0]valueToGo,inputdriveEnable);assign busLine = (driveEnable) ? valueToGo: 'bz;endmodulemodule slave#(parameter Asize = 5,Dsize = 16,Msize = 32)(inputrw,input [Asize-1:0] addressLines,inout [Dsize-1:0] dataLines,inputclock);regregreg[Dsize-1:0] m[0:Msize];[Dsize-1:0] internalData;enable;busDriver#(Dsize) bSlave (dataLines, internalData, enable);initialbegin("memory.data", m);enable = 0;endalways // bus slave endbegin@(negedge clock);if (~rw) begin //readinternalData <= m[addressLines];enable <= 1;@(negedge clock);enable <= 0;endLogic Level Modelingelse179//writem[addressLines] <= dataLines;endendmodulemodule master#(parameter Asize = 5,Dsize = 16)(output regrw,output reg [Asize-1:0] addressLines,inout[Dsize-1:0] dataLines,inputclock);regregenable;[Dsize-1:0] internalData;busDriver #(Dsize) bMaster (dataLines, internalData, enable);initialenable = 0;always // bus master endbegin#1wiggleBusLines (`READ, 2,0);wiggleBusLines (`READ, 3,0);wiggleBusLines (`WRITE, 2,5);wiggleBusLines (`WRITE, 3,7);wiggleBusLines (`READ, 2,0);wiggleBusLines (`READ, 3,0);endtask wiggleBusLines(inputreadWrite,input [Asize:0] addr,input [Dsize:0] data);beginrw <= readWrite;if (readWrite) begin// write valueaddressLines <= addr;internalData <= data;enable <= 1;endelse begin//read valueThe Verilog Hardware Description Language180addressLines <= addr;@ (negedge clock);end@(negedge clock);enable <= 0;endendtaskendmoduleExample 6.10 A Synchronous Bus Using Behavioral and Structural ConstructsResults of simulating Example 6.10 are shown in Figure 6.5.
It differs from theprevious simulation run (Figure 4.3) only in the fact that the data lines are z duringthe first clock cycle of a read bus cycle. Other than that, the two models produceidentical results.6.5 Logic Delay ModelingGate level modeling is used at the point in the design process when it is important toconsider the timing and functionality of the actual gate level implementation.
Thus, atthis point the gate and net delays are modeled, possibly reflecting the actual placement and routing of the gates and nets. In this section, we will concentrate on thelogic gate primitives and specifying their timing properties for simulation.Logic Level Modeling1816.5.1 A Gate Level Modeling ExampleThe tristate NAND latch shown in Example 6.11 illustrates the use of the bufif1 gateand detailed timing information. A diagram of the circuit is also shown in Figure 6.6.module triStateLatch(output qOut,input clock, data, enable);triqOut,notnand#5#(3,5)nand#(12,15)bufifl#(3,7,13)(ndata, data);d(wa, data, clock),nd(wb, ndata, clock);nq, wa),q, wb);qDrive (qOut, q, enable),nq, enable);endmoduleExample 6.11 A Tristate LatchThis latch drives its qOut andports, which are defined as tristate nets, whenthe enable input is one.
The bufif1 gate models the tristate functionality. As shown inTable 6.5, when the control input is 1, then the output is driven to follow the input.Note that a z on the data input is propagated as an unknown on the data output.When the control input is 0, the output is high impedance (z).182The Verilog Hardware Description LanguageIn the case where the control input is either x or z, the data output is modeled withL and H. L indicates the output is either a 0 or a z, and H indicates either a 1 or a z.Other tristate modeling primitives include bufif0 which reverses the sense of thecontrol input from bufif1, notif1 which inverts the data input and drives the outputwhen the control input is one, and notif0 which inverts the data input and drives theoutput when the control input is zero.
Truth tables for these gates may be found inAppendix D.The functionality of Example 6.11 may now be described. The basic latch functionis implemented by the cross-connected NAND gatesandWhen the clock islow, the outputs of d and nd are held high and the latch pair hold their value. Whenthe clock is high, then the d and nd values propagate through and change the latchvalue. TheandNAND gates follow the data input as long as the clock is high.The two bufif1 gates are driven by the output of the NAND latch gates and the inputenable signal. As per the definition of the bufif1 gate, when enable is high, the outputwill be driven.
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