Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 37
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Alternately, six delay values maybe given. Their order of specification is 0 to 1, 1 to 0, 0 to z, z to 1, 1 to z, z to 0. Inaddition, minimum, typical, and maximum delays may be specified for each of these.The formal syntax for specify blocks can be found in Appendix G.8. A set of system tasks, described in the simulator reference manual, allow for certain timingchecks to be made. These include, setup, hold, and pulse-width checks, and are listedwithin the specify block.Logic Level Modeling1896.7 Summary of Assignment StatementsWhen developing Verilog models of digital systems, an important aspect is capturinghow new values (outputs) are generated over time.
The book, so far, has presentedfour different methods for generating new values: gate primitives, continuous assignment, procedural assignment (“=”), and non-blocking assignment (“<=”). Within theVerilog language, these four methods fall into two major categories that differ in theway in which outputs are generated over time. Thus we call them timing models.These models are the gate-level timing model and the procedural timing model.The gate-level timing model is illustrated by the gate primitive (e.g., Example 6.1)and continuous assignment (e.g., Example 6.4).
When writing a simple AND expression, we could write either:and(a, b, c);orassign a = b & c;These two statements as shown are equivalent; both perform a bitwise AND of b and c,and assign the result to a. The way to think about these statements is that any timeany of the inputs (b or c) changes, the output a is re-evaluated. Further, in both ofthese statements, a is a net.The procedural timing model uses procedural statements found in initial andalways blocks to generate new values.
Regular procedural assignment (“=”) was illustrated in Example 1.5 and non-blocking procedural assignment (“<=”) was illustratedin Example 1.7. The always block:always @(posedge clock)has two inputs (clock and D) and one outputIn contrast to the gate-level timingmodel, the procedural assignment is not sensitive to all of its inputs; only certain onesat certain times. Here, the always block is only sensitive to positive edge changes onclock. When the positive edge occurs,is updated with the value of D. However, ifD, another input to the always block changes, is not updated. Procedural modelsare only sensitive to the inputs they are explicitly waiting for.
Further, the left-handsides of all procedural assignments are registers or word-selects of memories.The loading of the value into the register or memory is done only when control istransferred to the procedural assignment statement. Control is transferred to a procedural assignment statement in a sequential manner, flowing from one statement to thenext.
In this way, procedural assignments function similar to a normal software programming language assignment statement. However, the flow of control can be inter-The Verilog Hardware Description Language190rupted by an event (@) statement (and as we’ll see later, wait and #delay statements),and then is only reactivated when the event occurs.The procedural assignments “=” and “<=” can be further categorized by when theleft-hand side is updated. The “=” updates its left-hand side immediately so that thisnew value is available in the next procedural statement. In contrast, “<=” updates itsleft-hand side only after all of the right-hand sides of “<=” statements waiting on thesame edge in the whole design have been calculated.
Thus, the new value on the lefthand side is not available in the next procedural statement. This leads to anomalousdescriptions such as:@(posedge clock) begin // somewhere in an evil always blockm = 3;n = 75;n <= m;r = n;...The question is what value is assigned to r? The answer is 75. Even though the thirdstatement changes r to 3, the left-hand side isn’t updated immediately. Indeed thealways block doesn’t stop (i.e., block) to update n; rather it keeps going (thus the namenon-blocking), using the value of n from before the clock edge. Eventually, n will beupdated with the value of 3, but only after all other right-hand sides of non-blockingassignments have been evaluated.
It’s better not to write models such as the evil oneabove; they are hard to read. Further, they are not accepted by synthesis tools, so theiruse is limited. Use non-blocking assignments when describing concurrent transfers inedge-sensitive systems.In essence, the two timing models are closely aligned with the two fundamentaldata types of the language: nets and registers.
Continuous assigns and primitive gatesmay only drive nets, and procedural assignments may only be made to registers (andmemories).References: procedural assignment 3.1; continuous assignment 6.3; timing models 8.16.8 SummaryThis chapter has covered the basics in logic level modeling using the Verilog language.We have seen how to define gates and nets and interconnect them into more complexmodules. The use of delays and strengths have been illustrated, and we have shownhow module definitions can be parameterized.Logic Level Modeling1916.9 Exercises6.1Write a module with the structure:module progBidirect (ioA, ioB, selectA, selectB, enable);inout [3:0] ioA, ioB;input [1:0] selectA, selectB;inputenable;...endmodulesuch that selectA controls the driving of ioA in the following way:selectA0123ioAno drivedrive all 0'sdrive all 1'sdrive ioBand selectB controls the driving of ioB in the same way.
The drivers are only to be ineffect if enable is 1. If enable is 0 the state of the ioA and ioB drivers must be highimpedance.A. Write this module using gate level primitives only.B. Write this module using continuous assignments only.Change the Hamming encoder/decoder in Example 6.3 so that random individual bits are set for each data item passed through the noisy channel.6.3 Use the array-of-instances construct to specify a multi-bit full adder. The module header is:6.2192The Verilog Hardware Description Languagemodule fullAdder (cOut, sum, a, b, cIn);A. Describe this as an 8-bit adder where sum, a, and b are 8-bit elements andcOut and cIn are one-bit inputs.B.
Parameterize the bit-width of elements sum, a, and b of module fullAdder.The Hamming encoder/decoder in Example 6.3 detected and corrected oneerror bit. By adding a thirteenth bit which is the exclusive-OR of the othertwelve bits, double bit errors can be detected (but not corrected). Add this feature to the example and modify the noisy channel so that sometimes two bits arein error. Change thestatement to indicate the double error.6.5 Change the memory in Example 6.10 to use the double bit detector/single bitcorrector circuit from the previous problem. Change the system data size to be 8bits. When a word is written to memory, it should be stored in encoded form.When it is read, it should be decoded and corrected. Add a bus line driven bythe slave and read by the master that indicates when a double error hasoccurred.
Devise a means for the data in the memory to become corrupted, anda means of displaying when a double error has occurred.6.6 Use the array-of-instances construct to specify a multi-bit full adder. The module header is:module fullAdder (cOut, sum, a, b, cIn);6.4A. Describe this as an 8-bit adder where sum, a, and b are 8-bit elements andcOut and cIn are one-bit inputs.B.
Parameterize the bit-width of elements sum, a, and b of module fullAdder.6.7 The following combinational logic block has three inputs and an output. Thecircuit was built in some screwy technology and then analyzed. We now want toinsert the correct input-to-output timing information into the circuit (internalnode timings need not be correct).Here are the circuit timings that must be represented in the circuit.The delay of a rising or falling edge on a or b to output f: 15 time unitsThe delay of a rising or falling edge on c to output f: 10 time unitsYes, those times are rather strange given the logic diagram.
However, this is ascrewy technology and the transistor implementation made for some strange,but actual, time delays.Logic Level Modeling193Assume a, b, and c are outputs of synchronously clocked flip flops. Write thestructural Verilog description that will be correct in functionality and timing.7Cycle-AccurateSpecificationWe now turn our attention to a higher level of modeling: cycle accurate, sometimescalled scheduled behavior. At this level, a system is described in a clock-cycle by clockcycle fashion, specifying the behavior that is to occur in each state.
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