Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 36
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When enable is low, the output will be z.References: Verilog gates D; nets 6.2; delays across a module 6.66.5.2 Gate and Net DelaysGate, continuous assign, and net delays provide a means of accurately describing thedelays through a circuit. The gate delays describe the delay from when the inputs of agate change until when the output of the gate is changed and propagated. Continuousassign delays describe the delay from when a value on the right-side changes to whenthe left-hand side is changed and propagated.
Net delays describe the delay fromwhen any of the net’s driving gates or assign statements change to when the value ispropagated. The default delay for gates, nets, and assign statements is zero. If onedelay parameter is specified, then the value is used for all propagation delays associated with the gate, net, or assign.Logic Level Modeling183The following gate instantiations are excerpts from Example 6.11 and will be usedto illustrate the different propagation situations.notnand#5#(12,15)(ndata, data);nq, wa),q, wb);bufif1 #(3,7,13) qDrive (qOut, q, enable),nq, enable);Propagation delays are specified in terms of the transition to 1, the transition to 0,and the transition to z (turn-off delay). The NOT gate has been specified with a delayof 5.
Since only this one value is given, the delay will pertain to both the transition to1 and the transition to 0. The NAND gate instances have a rising delay of 12 and a falling delay of 15. Finally, the bufif1 gates have a rising delay of 3, falling delay of 7, anda delay to the high impedance value of 13. Note that if the gate is in the high impedance condition, then when the enable becomes 1, it will take 3 time units (i.e. the rising delay) for the output to change to 1.Generally speaking, the delay specifications takes the form of#(dl, d2)or#(dl, d2, d3)where d1 is the rising delay, d2 the falling delay, and d3 the delay to the high impedance value. The reason for the two-specification form is that some gates allow onlytwo times to be specified and some allow three.
A special case of the meaning of d3 iswhen it is used with the trireg net; d3 is then the decay time at which point the wire’svalue becomes x. Delay specification may be summarized in the following syntax:delay2|# delay_value# ( delay_value [, delay_value] )|# delay_value# (delay_value [, delay_value [, delay_value ] ] )delay3delay_valueunsigned_number| parameter_identifier| mintypmax_expressionmintypmax_expressionexpressionThe Verilog Hardware Description Language184| expression : expression : expression(Note that the second form of mintypmax_expression will be discussed insection 6.5.1.) Table 6.6 summarizes the from-to propagation delay used by the simulator for the two and three delay specifications.
Again, if no delay specification ismade, zero is the default. If only one value is given, then all of the propagations areassumed to take that time.A shorthand for remembering some of the delays is that a rising delay (d1) is from0 to x, x to 1, or z to 1. Likewise, a falling delay is from 1 to x, x to 0, or z to 0.The tri net defined in Example 6.11 does not include its own delay parameters.However, it could have been defined as:tri#(2,3,5)qOut,In this case, any driver that drives either of these nets would incur a rising delay of 2,a falling delay of 3, and a delay to z of 5 before its output would be propagated.
Thusin Example 6.11 with the bufifl qDrive gate instance driving the qOut net, the risingdelay from when an input to gate qDrive changes to when the result is propagated onthe qOut net is 5 (2 + 3), the falling delay is 10, and the delay to z is 18.If the case of a continuous assign where the left-hand side is a vector, then multipledelays are handled by testing the value of the right-hand side. If the value was nonzero and becomes zero, then the falling delay is used. If the value becomes z, then theturn-off delay is used.
Otherwise, the rising delay is used.Logic Level Modeling185References: delays across a module 6.66.5.3 Specifying Time UnitsOur examples have used the # delay operator to introduce time into the simulationmodels of hardware components. However, time units for the delay values have notbeen specified. The `timescale compiler directive is used to make these specifications.The form of the compiler directive is:`timescale<time_unit> / <time_precision>This directive sets the time units and precision for the modules that follow it. Multiple `timescale directives may be included in a description.The <time_unit> and <time_precision> entries are an integer followed by a unit oftime measure. The integer may be one of 1, 10, or 100.
The time measure abbreviations are shown in Table 6.7. Thus a module following a `timescale directive of:`timescale10 ns / 1 nsmaintains time to the precision of 1 nanosecond. The values specified in delaysthough are multiples of 10 nanoseconds. That is, #27 means delay 270 nanoseconds.Table 6.8 shows several examples of delay specifications and the actual time delayedfor a given `timescale directive. The simulation times are determined by rounding tothe appropriate number of decimal places, and then multiplying by the time unit.The Verilog Hardware Description Language1866.5.1 Minimum, Typical, and Maximum DelaysVerilog allows for three values to be specified for each ofthe rising, falling, and turnoff delays. These values arethe minimum delay, the typical delay, and the maximumdelay.Example 6.12 shows theuse of the minimum, typical,and maximum delays beingseparated by colons, and therising, falling, and turn-offdelays being separated bycommas.module IOBuffer#(parameterR_Min = 3, R_Typ = 4, R_Max = 5,F_Min = 3, F_Typ = 5, F_Max = 7,Z_Min = 12, Z_Typ = 15, Z_Max = 17)(inout bus,input in,output out,input dir);bufif1 #(R_Min: R_Typ: R_Max,F_Min: F_Typ: F_Max,Z_Min: Z_Typ: Z_Max)(bus, out, dir);buf#(R_Min: R_Typ: R_Max,F_Min: F_Typ: F_Max)(in, bus);endmoduleGenerally, the delay speciExample 6.12 Illustration of Min, Typical, and Maxfication formDelays.#(d1, d2, d3)is expanded to:#(d1_min: d1_typ: d1_max, d2_min: d2_typ: d2_max, d3_min: d3_typ: d3_max)This is the second form of mintypmax_expression shown in the formal syntax specification of the previous section.Logic Level Modeling187Min/Typ/Max delays may be used on gate primitives, nets, continuous assignments, and procedural assignments.6.6 Delay Paths Across a ModuleIt is often useful to specify delays to paths across a module (i.e.
from pin to pin), apartfrom any gate level or other internal delays specified inside the module. The specifyblock allows for timing specifications to be made between a module’s inputs and outputs. Example 6.13 illustrates the use of a specify block.module dEdgeFF(input clock, d, clear, preset,output q);specify// specify parametersspecparam// module path declarations(clock => q) =(clear, preset *> q) =endspecify// description of module's internalsendmoduleExample 6.13 Delay Path Specifications.A specify block is opened with the specify keyword and ended with the endspecifykeyword. Within the block, specparams are declared and module paths are declared.The specparams name constants that will be used in the module path declarations. Themodule path declarations list paths from the module’s inputs and inouts (also calledthe path’s source), to its inouts and outputs (also called the path’s destination).
The timing specified will be used for all instances of the module.In this example, the first module path declaration specifies that the rising delaytime from the clock input to the q output will be 100 time units and that the fall timewill be 120. The second module path declaration specifies the delays from both clearand preset to q. Delay paths are not typically mixed with delay (#) operators in a mod-The Verilog Hardware Description Language188ule description. However, if they are, then the maximum of the two delays will beused for simulation.Two methods are used to describe the module paths, one using “=>” and the otherusing “*>”.
The “=>” establishes a parallel connection between source input bits and destination output bits. The inputs and outputs must have the same number of bits. Eachbit in the source connects to its corresponding bit in the destination.The “*>” establishes a full connection between source inputs and destination outputs.Each bit in the source has a path to every bit in the destination.
The source and destination need not have the same number of bits. In Example 6.13, we specify that clearand preset have a path to the q output. Multiple outputs may be specified. So, forinstance, we could state:(a,b*>c,d) = 10;This statement is equivalent to:(a=>c) = 10;(a => d) = 10;(b => c) = 10;(b => d) = 10;Here, we assume that a, b, c, and d are single bit entities.
We could also state:(e => f) = 10;If e and f were both 2-bit entities, then this statement would be equivalent to:(e[l] => f[l]) = 10;(e[0] => f[0]) = 10;Module paths may connect any combination of vectors and scalars, but there aresome restrictions. First, the module path source must be declared as a module input orinout. Secondly, the module path destination must be declared as an output or inout,and be driven by a gate level primitive other than a bidirectional transfer gate.The delays for each path can be specified as described in the previous section,including the capability of specifying rising, falling, and turn-off delays, as well asspecifying minimum, typical, and maximum delays.
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