Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 28
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However, since a branch is being executed, this instruction and theincremented pc are not needed. A separate indicator register, skip, is set by the execution stage to indicate that a branch occurred and that the next instruction should befetched from m[pctemp] rather than from m[pc]. Additionally, since the instructionafter the branch was already fetched, skip also controls the execution stage to keep itfrom being executed.In this example, all assignments are non-blocking except one. In the fetch process,pc is assigned with a blocking assignment so that it can be used on the following linesof the process.There are alternate approaches to correcting this problem, including duplicatingthe case(ir) statement in the fetch stage so that pc is conditionally loaded with abranch target when a branch occurs.
However, the execution stage will still need toskip the extra instruction.Concurrent Processesmodule mark1PipeStage;reg[15:0]signedreg [12:0]signedreg [12:0]signedreg [15:0]reg131m [0:8191];pc;acc;ir;ck, skip;always @(posedge ck) beginif (skip)pc = pctemp;ir <= m [pc];pc <= pc + 1;end//signed 8192 x 16 bit memory// signed 13 bit program counter// signed 13 bit accumulator// 16 bit instruction register//fetch processalways @(posedge ck) begin//execute processif (skip)skip <= 0;elsecase (ir [15:13])3'b000: beginpctemp <= m [ir [12:0]];skip <= 1;end3'b001: beginpctemp <= pc + m [ir [12:0]];skip <= 1;end3'b010 : acc <= -m [ir [12:0]];3'b011: m [ir [12:0]] <= acc;3'b100,3'b101: acc <= acc - m [ir [12:0]];3'b110: if (acc < 0) beginpctemp <= pc + 1;skip <= 1;endendcaseendendmoduleExample 4.10 Synchonization Between the Stages132The Verilog Hardware Description Language4.6 Disabling Named BlocksIn Example 3.4, we showed how thedisable statement could be used tobreak out of a loop or continue executing with the next iteration of theloop.
The disable statement, using thesame syntax, is also applicable in concurrent process situations. Essentially, the disable statement may beused to disable (or stop) the executionof any named begin-end block —execution will then continue with thenext statement following the block.The block may or may not be withinthe process containing the disablestatement. If the block being disabledis not within the local or upwardscope, then hierarchical names arerequired.To illustrate disabling a concurrentprocess we return to the scheduledbehavior in Example 4.11.
A resetinput has been added, along with aninitial statement, and a wait statementin the always block. These additionsprovide an asynchronous, assertedlow, reset for this cycle-accurate specification.module simpleTutorialWithReset(inputclock, reset,output reg [7:0] y,x);initialforever begin@(negedge reset)disable main;endalways begin: mainwait (reset);@(posedge clock) x <= 0;i = 0;while (i <= 10) begin@(posedge clock);x <= x + y;i = i + 1;end@(posedge clock);if (x<0)y<=0;else x <= 0;endendmoduleExample 4.11 Description UsingScheduled Behavioral ApproachConsider how the module works. At the start of time, both the initial and alwaysblock can begin executing.
One stops to wait for a negative edge on reset while theother waits for reset to be TRUE. If we assume that reset is unasserted (1), then thealways block will begin executing its cycle-accurate specification. At some time, resetis asserted (i.e., it becomes 0), and its negative edge activates the initial block. Theinitial block disables main, which is the name of the begin-end block in the alwaysblock. No matter where the main block was in its execution, it is exited, and thealways block is restarted. The first statement at the start is a wait for reset to be TRUE— unasserted. Thus, when reset is asserted, the main block is stopped, and it does notrestart at the beginning until reset becomes unasserted.A block is named as illustrated in the example.
A block declaration is a statementand has the general form:Concurrent Processes133statementseq_blockseq_blockbegin [: block_identifier {block_item_declaration} ]{ statement }endblock_item_declarationparameter_declarationlocal_parameter_declarationinteger_declarationreal_declarationtime_declarationrealtime_declarationevent_declarationNote that the introduction of a named block also allows for the optional block declarations. At this point, other parameters and registers may be defined for the scope ofthe block.The action of the disable statement not only stops the named block, but also anyfunctions or tasks that have been called from it.
Also, any functions or tasks they havecalled are also stopped. Execution continues at the next statement after the block. Ifyou disable the task (or function) you are in, then you return from the task (or function).It is also interesting to point out what is not stopped by the disable statement. Ifthe disabled named block has triggered an event control, by changing a value or bytriggering a named event, the processes watching for these events will already havebeen triggered. They will not be stopped by the disable.When we defined the term process, we emphasized that it referred to an independent thread of control.
The implementation of the control was irrelevant; it could beas a microcoded controller, simple state machine, or in some other way. In the case ofExample 4.11, if we assume that the first state of the controller implementing thealways statement is encoded as state zero, then the initial block could be implementedas an asynchronous reset of the state register of the always’ controller. That is, the initial statement would not look like a state machine, rather it would be some simplereset logic. The point is that regardless of the implementation of the two processes,there are two independent activities in the system capable of changing state. Each isactive and operating independently of the other.References: always 3.1; disable in loops 3.3.2; parallel blocks 4.9; hierarchical names 3.6; scope ofidentifiers 3.6The Verilog Hardware Description Language1344.7 Intra-Assignment Control and Timing EventsMost of the control and timing events that we have used in examples have been specified to occur before the action or assignment occurs.
We have written statements like:#25 a = b;or@(posedge w) q = r;The actions performed respectively are: delay 25 time units and then assign the valueof b to a; and delay until there is a positive edge on w and then assign the value of r toq. What is common about these behavioral statements is the “delay” (either the # orthe @) occurs before the assignment is performed. Indeed, the right-hand side of thestatement is not evaluated until after the “delay” period. Intra-assignment timing controls allow for the “delay” to occur within the assignment — between when the righthand side is evaluated and when the left-hand side is assigned. Conceptually, theseassignments have a master-slave character; inputs are sampled, a delay occurs, andthen later the outputs are assigned.The assignments are written with the delay or event control specification in themiddle of the assignment just following the “=”.
This makes intuitive sense whenreading such an assignment. Given that the right-hand side of the equation is evaluated first and then assigned to the left-hand side, having the delay or event control inthe middle of the assignment keys the reader that you must delay before completingthe right-to-left assignment. Although all of our examples here are with blockingassignments, intra-assignment control and timing events can be used with non-blocking assignments as well.
The intra-assignment timing control versions of the statements above are:Concurrent Processes135The actions taken by the first two assignments are respectively: evaluate b and storethe value in a temporary place, delay 25 time units, and then assign the stored value toa; and evaluate r and store the value in a temporary place, wait for the next positiveedge on w, and then store the temporary value in q. These correspond to the illustrations above.
The third entry shows the intra-assignment repeat which was not illustrated above. The right-hand side is calculated and assigned to a temporary place.When the delay is completed (in this case, waiting for two positive edges of clock),the value is assigned to w. Thus each of these statements stores a temporary copy ofthe right-hand-side value for assignment to the left-hand side at a later time.The copy of the right-hand side is actually stored in the simulator event queue andis not accessible for any other purposes.The three forms of the intra-assignment statement, for both blocking and nonblocking assignments, are described below:statementblocking_assignment;nonblocking_assignment;blocking_assignmentvariable_1value = [ delay_or_event_control ] expressionnonblocking_assignmentvariable_1value <= [ delay_or_event_control ] expressiondelay_or_event_controldelay_controlevent_controlrepeat (expression ) event_controldelay _control# delay_value# ( mintypmax_expression )The Verilog Hardware Description Language136event_control@ event_identifier@ (event expression)@*@(*)event_expressionexpressionhierarchical_identifierposedge expressionnegedge expressionevent_expression or event_expressionevent_expression, event_expressionA use of intra-assignment timing controls is specifying a D flip flop.
This approachuses the statement:@(posedge clock) q = #10 d;This statement provides a master-slave character to the behavior of the flip flop. Thismodel samples the value of d at the clock edge and assigns it 10 time units later. However, the following does not accurately model a flip flop.q = @(posedge clock) d;This statement samples the value of d whenever the statement is executed. Thenwhen the positive edge of the clock occurs, q is assigned that value. Given that theinitial value of d could be sampled well before the time of the clock edge, the typicalbehavior of a flip flop is not captured.References: non-determinism 8.34.8 Procedural Continuous AssignmentThe continuous assignment statement presented in an earlier chapter, allows for thedescription of combinational logic whose output is to be computed anytime any oneof the inputs change.
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