Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 24
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That is, they are edge-sensitive. When control passes to one ofthese statements, the initial value of the input being triggered on is checked. Whenthe value changes later (for instance, when a positive edge on the value has occurred),then the event control statement completes and control continues with the next statement.This section covers two basic forms of the event control: one that watches for avalue change, and another, called the named event, that watches for an abstract signalcalled an event.The Verilog Hardware Description Language1124.2.1 Event Control StatementExample 4.2 will be used to motivatethe discussion of event control statements. In this example, the statement:@(negedge clock) q <= data;module dEdgeFF(output reg q,inputclock, data);always@(negedge clock) q <= data;endmodulemodels the negative edge triggering of aD-type flip flop. This procedural eventcontrol statement watches for the negative transition of clock and then assigns Example 4.2 AD-Type Edge-TriggeredFlip Flopthe value of data to q.
The valueassigned to q is the value of data just before the edge of the clock.In addition to specifying a negative edge to trigger on, we may also specify a positive edge (“posedge”) or make no specification at all. Consider:@ (ricky) lucy = crazy;Here, lucy will be loaded with the value crazy if there is any change on ricky.The general form of the event control statement is:event_control@ event_identifier|@ (event_expression)|@*|@ (*)event_expressionexpressionhierarchical_identifier|posedge expression||negedge expressionevent_expression or event_expression|event_expression, event_expression|The constructs, @* and @(*), are used for specifying sensitivity lists when synthesizingcombinational circuits. The qualifier may be “posedge”, “negedge”, or it may be leftblank.
The expression is a gate output, wire, or register whose value is generated as aresult of activity in another process. The event control begins watching for the specified change from the time procedural control passes to it. Changes prior to the timewhen control passed to the event control statement are ignored. After the eventoccurs, the statement is executed. If, while waiting for the event, a new value for theexpression is generated that happens to be the same as the old value, then no eventoccurs.Concurrent Processes113At times, the event control expression may take on unknown values. In such cases,a negative edge is defined as a transition from 1 to 0,1 to x, or x to 0. A positive edgeis defined as a transition from 0 to 1,0 to x, or x to 1.Any number of events can be expressed in the event control statement such that theoccurrence of any one of them will trigger the execution of the statement.
A time-outexample is shown in Example 4.3.alwaysbegin// start the timer that will produce the timeOut signal;@(posedge inputA, posedge timeOut)if (timeOut)// … error recoveryelse regA = regB;// normal operation//…other statementsendExample 4.3 ORing Two Events in an Event Control StatementIn this example, we are watching for either of two events, a positive edge on inputA,or a positive edge on timeOut. The two events are specified in a comma-separatedlist.
In this case, we can trigger on the intended event — the change on inputA.However, if the InputA event does not occur with a reasonable amount of time, theprocess can extricate itself from a deadlock situation and begin some form of errorrecovery.The comma-separated event list is important in concurrent process applications(the BNF also allows for the list to be or-separated).
If a process needs to wait for anyof several events to occur, it does not want to prematurely commit itself to waiting forone specific event before waiting for another. Indeed, since the events may not occurin a given sequential order — the order of arrival may be data dependent — waitingfor individual events in a specific sequential order will probably cause the system todeadlock. That is, one process will be waiting for an event that will never occur. Thecomma-separated event list allows us to wait for any of several events.References: level sensitive wait 4.3; compare event and wait 4.3.3; intra-assignment delay 4.74.2.2 Named EventsThe event control statements described above require that a change be specifiedexplicitly. A more abstract version of event control, the named event, allows a triggerto be sent to another part of the design. The trigger is not implemented as a registerThe Verilog Hardware Description Language114or wire and thus is abstract in nature.
Further, even if it crosses module boundaries, itrequires no port specification. Other parts of the design may watch for the occurrenceof the named event before proceeding.Example 4.4 shows a Fibonacci number generator example using a named event tocommunicate between the two modules. The topFib module instantiates only twomodules (fnc and ng).The always statement in module numberGen illustrates the triggering of eventready:#50ready;The event must have been previously declared as on the fourth line of the moduledescription. The always statement will continuously delay for 50 time units, increment the value number, delay for 50 more time units, and then trigger event ready.Module fibNumCalc watches for the event on the first line of its always statement:@ng.readycount = startingValue;The name “ng.ready” is a hierarchical name for event ready and will be explained afterwe dispense with how the named event works.
For module fibNumCalc to receive thetrigger, it must first have started to execute the @event statement, and then the triggerstatement in module numberGen must be executed. At this time, module fibNumCalc will continue executing with the statement count= startingValue;.Note that the act of triggering an event is, itself, a statement and need not be combined with a delay operator as in the example. The general form for activating thenamed event is:statementevent_triggerevent_triggerhierarchical_event_identifier;This description of the Fibonacci number generator does have a race condition in itif module fibNumCalc takes longer than 100 time units to execute the always loop.Module numberGen produces a value every 100 time units and sends a trigger.
Ifmodule fibNumCalc did not get around its always loop in less than that time, itwould miss numberGen’s trigger. The result would be that the Fibonacci number ofevery other number produced by numberGen would be calculated.Concurrent Processesmodule topFib;wire [15:0]numberGenfibNumCalcendmodule115number, numberOut;ngfnc(number);(number, numberOut);module numberGen(output reg [15:0] number = 0);eventready;//declare the eventalwaysbegin#50 number = number + 1;#50 ready;//generate event signalendendmodulemodule fibNumCalc(input[15:0] startingValue,output reg [15:0] fibNum);reg[15:0] count, oldNum, temp;alwaysbegin@ng.ready//wait for event signalcount = startingValue;oldNum = 1;for (fibNum = 0; count != 0; count = count - 1)begintemp = fibNum;fibNum = fibNum + oldNum;oldNum = temp;end("%d, fibNum=%d",fibNum);endendmoduleExample 4.4 Fibonacci Number Generator Using Named Events116The Verilog Hardware Description LanguageNote that there is no register to hold the trigger, nor any wire to transmit it; ratherit is a conceptual event which when it occurs in one module, can trigger other modules that were previously stopped at an @event statement.
Further, the named event ismore abstract than the event control in that no hardware implementation clues aregiven. By comparison, a posedge event control implies that some form of edge triggering logic will be used to detect that such a transition has occurred. The namedevent is typically used in simulation.References. Hierarchical names 3.64.3 The Wait StatementThe wait statement is a concurrent process statement that waits for its conditionalexpression to become TRUE.
Conceptually, execution of the process stops until theexpression becomes TRUE. By definition, the conditional expression must include atleast one value that is generated by a separate, concurrent process — otherwise, theconditional expression would never change. Because the wait must work with inputsfrom other processes, it is a primary means of synchronizing two concurrent processes.The wait statement condition is level-sensitive. That is, it does not wait for achange in a value. Rather it only checks that the value of the conditional is TRUE.
If itis, execution continues. If it is FALSE, the process waits.The wait is often used in handshakingmodule consumersituations where we are synchronizing(input [7:0] dataIn,two processes. Example 4.5 illustrates theinputready);situation where a process will only readthe dataIn input if the ready input isreg[7:0] in;TRUE. The wait synchronizes the two processes by insuring that the consumer proalwayscess does not pass the wait statement andbeginconsume the data until the producer prowait (ready)cess generates dataIn and sets the readyin = dataIn;signal to TRUE.
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