Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 19
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Four differentstatements are provided, including the repeat, for, while, and forever loops.3.3.1 Four Basic Loop StatementsAn excerpt from Example 3.1 illustrated in Example 3.2 shows the use of the repeatloop. In this form of loop, only a loop count is given in parentheses after the keywordrepeat (`DvLen) beginquotient = quotient << 1;dividend = dividend << 1;dividend[`DdLen-1:`HiDdMin] =dividend[`DdLen-1:`HiDdMin] - divisor;if (! dividend [`DdLen-1])quotient = quotient + 1;else dividend[`DdLen-1:`HiDdMin] =dividend[`DdLen-1:`HiDdMin] + divisor;endExample 3.2 An Excerpt from Example 3.1repeat. The value of the loop count expression is determined once at the beginning ofthe execution of the loop. Then the loop is executed the given number of times. Theloop count expression is sampled once at the beginning of the loop, and thus it is notpossible to exit the loop execution by changing the loop count variable.
The disablestatements described later allow for early loop exits.The general form of the repeat statement is:statementloop_statementBehavioral Modeling83loop_statementrepeat ( expression ) statementThe loop in Example 3.2 could have been written as a for loop as:for (i = 16; i; i = i - 1)begin…//shift and subtract statementsendIn this case, a register must be specified to hold the loop counter. The for loop is verysimilar in function to for loops in the C programming language.
Essentially, this forloop initializes i to 16, and while i is not zero, executes the statements and then decrements i.The general form of the for loop isloop_statementfor (variable_assignment; expression; variable_assignment) statementSpecifically, the first assignment is executed once at the beginning of the loop. Theexpression is executed before the body of the loop to determine if we are to stay in theloop. Execution stays in the loop while the expression is TRUE.
The second assignment is executed after the body of the loop and before the next check for the end ofthe loop. The statement is the body of the loop. The difference between the for andrepeat loop statements is that repeat is simply a means of specifying a constant number of iterations. The for loop is far more flexible and gives access to the loop updatevariable for control of the end-of-loop-condition.As in the C programming language, the above for statement could have been written using a while statement as:i = 16;while (i)begin… // shift and subtract statementsi = i-1;endThe general form of the while isloop_statementwhile (expression) statementThe Verilog Hardware Description Language84The expression is evaluated and if it is TRUE, the statement is executed.
The whileexpression is then evaluated again. Thus, we enter and stay in the loop while theexpression is TRUE.The while expression must be updated as part of the loop statement execution, inthis case “i = i - 1”. The while statement cannot be used to wait for a change in a valuegenerated external to its always statement as illustrated in the following example.module sureDeath(input inputA);//This will not work!!alwaysbeginwhile (inputA);// wait for external variable// other statementsendendmoduleHere, the while statement expression is dependent on the value of inputA and thewhile statement is null. The above while statement appears to have the effect of doingnothing until the value of inputA is TRUE, at which time the other statements are executed. However, since we are waiting for an external value to change, the correctstatement to use is the wait.
For further discussion, see section 4.3 on the wait statement.Finally, the forever loop loops forever. An example of its use is in the abstractdescription of a microprocessor. Here we see that certain initializations occur only atpower-on time. After that, we remain in the forever loop fetching and executingmodule microprocessor;alwaysbeginpowerOnInitializations;foreverbeginfetchAndExecuteInstructions;endendendmoduleExample 3.3 An Abstract MicroprocessorBehavioral Modeling85instructions. A forever loop may be exited by using a disable statement, as will be discussed in the next section. If the forever loop is exited, then the always statement willstart the power-on initializations and begin the forever loop again.The general form of the forever loop is:loop_statementforever statementReferences: disable 3.3, 4.6; wait 4.3; comparison with wait 4.3.2; intra-assignment repeat 4.73.3.2 Exiting Loops on Exceptional ConditionsGenerally, a loop statement is written to execute to a “normal” exit; the loop counter isexhausted or the while expression is no longer TRUE.
However, any of the loop statements may be exited through use of the disable statement. A disable statement disables, or terminates, any named begin-end block; execution then begins with thestatement following the block. Begin-end blocks may be named by placing the nameof the block after a colon following the begin keyword. An example of the C programming statements break and continue are illustrated in Example 3.4.begin :breakfor (i = 0; i < n; i = i + 1)begin: continueif(a==0)disable continue;… // other statementsif (a = = b)disable break;… // other statementsendend// proceed with i = i + 1// exit for loopExample 3.4 Break and Continue Loop ExitsExample 3.4 shows two named blocks, break and continue.
Recall that the continue statement in C skips the rest of the loop body and continues the loop with theloop update, and that the break statement breaks out of the loop entirely, regardless ofthe loop update and end-of-loop condition. The disable statements in the exampleperform the analogous actions. Specifically, the disable continue statement stops execution of the begin-end block named continue and passes control to the update of thefor loop. The disable break statement stops execution of the block that contains thefor loop. Execution then proceeds with the next statement.The Verilog Hardware Description Language86The general form of the disable statement is:statementdisable_statementdisable_statementdisable hierarchical_task_identifier;disable hierarchical_block_identifier;References: disable named blocks 4.6; tasks 3.53.4Multi-way BranchingMulti-way branching allows the specification of one or more actions to be taken basedon specified conditions.
Verilog provides two statements to specify these branches: ifelse-if, and case.3.4.1 If-Else-IfIf-else-if simply uses if-then-else statements to specify multiple actions. It is the mostgeneral way to write a multi-way decision in that it allows for a variety of differentexpressions to be checked in the if conditional expressions. Consider the descriptionof a simple computer shown in Example 3.5. The example is reminiscent of the earlyMark-1 computer (a few details have been changed) and is used here for its simplicity.A cycle-accurate style of specification is used, separating the instruction fetch andexecution into two separate clock periods. A memory m is declared with 8192 16-bitwords.
The memory, accumulator, and program counter are declared to be signedgiven that they will store signed data.This example uses the if-else-if statement to specify the instruction decode of thecomputer. Bits fifteen through thirteen of the instruction register (ir[l5:13]) are compared with seven of the eight possible combinations of three bits.
The one thatmatches determines which of the instructions is executed.References: if-then-else 3.2; conditional operator 3.2.23.4.2 CaseThe case statement can be used for multi-way branches when each of the if conditionals all match against the same basic expression. In Example 3.6, the Mark-1 description is rewritten using the case statement for instruction decoding.Behavioral Modelingmodule mark1;reg [15:0]reg [12:0]reg [12:0]reg [15:0]reg87signedsignedsignedm [0:8191];pc;acc;ir;ck;// signed 8192 x 16 bit memory// signed 13 bit program counter// signed 13 bit accumulator// 16 bit instruction register// a clock signalalwaysbegin@(posedge ck)ir <= m [pc];// fetch an instruction@(posedge ck)if (ir[15:13] = = 3'b000)// begin decodingpc <= m [ir [12:0]];//and executingelse if (ir[15:13]==3'b001)pc <= pc + m [ir [12:0]];else if (ir[15:13]==3'b010)acc <= -m [ir [12:0]];else if (ir[15:13] == 3'b011)m [ir [12:0]] <= acc;else if ((ir[15:13] == 3'b101) || (ir[15:13] == 3'b100))acc <= acc - m [ir [12:0]];else if (ir[15:13] == 3'b110)if (acc < 0) pc <= pc + 1;pc <= pc + 1;//increment program counterendendmoduleExample 3.5 The Mark-1 Processor With If-Else-IfThe case expressions are evaluated linearly in the order given in the description.
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