Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 18
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Thesetwo signals are the handshake signals that allow the divide module to communicateand synchronize with other modules. done indicates when the divide module hascompleted a division and stored the result in the quotient. Since at the beginning noquotient has been calculated, done is set to FALSE (or zero). Then we wait for the goinput to be one (or TRUE) signifying that the dvInput and ddInput inputs are valid.When go becomes TRUE, dvInput and ddInput are copied into divisor and dividendrespectively.The wait statement, waits for an external condition to become TRUE.
When it isexecuted, execution continues if the condition in the parentheses is TRUE. However, ifthe condition is FALSE, the always block stops executing and waits for the condition tobecome TRUE. At that point, execution continues with the statement after the wait.The wait statement is discussed further in section 4.3.The first example of an if tests whether the divisor is zero or not with the statement:if (divisor)begin// … statementsendThis shows the basic form of the if statement. The if is followed by a parenthesizedexpression; a zero expression evaluates to FALSE and any value other than zero evaluates to TRUE.
Comparison with an unknown (x) or high impedance (z) may produce aresult that is either unknown or high impedance; these are interpreted as FALSE. Inthis case, we are testing the divisor. If it is not zero, then we follow the normal dividealgorithm. The begin-end block following the if statement allows all of the encompassed statements to be considered as part of the then statement of the if.More formally:statementconditional _statement|conditional_statementif (expression) statement_or_null [ else statement_or_null ]Continuing with the divide algorithm, the absolute value of each of the inputs isdetermined and their original signs are saved.
More specifically, the statementsThe Verilog Hardware Description Language78negDivisor = divisor[`DvLen-1];if (negDivisor)divisor = - divisor;first assign bit DvLen-1 (i.e., bit 15) of the divisor to negDivisor. If this bit is a one,indicating that the value was negative in the two’s complement number representation, then the then part will be executed and divisor will be negated, making it positive. It should be noted that since there is no begin-end block with this if, the thenstatement is the first statement (up to the semicolon) following the if.This statement also illustrates a bit-select. A bit-select is used to specify that onlyone of the bits of a vector are to be used in the operation.
A range of bits may also bespecified by separating the bit numbers specifying the range with a colon. This iscalled a part-select. Also, a starting bit number and a width may be specified. The +shown below indicates the bit numbers increase from the starting but number; the indicates the bit numbers decrease. More formally, a bit- or part-select occurs eitheras an expression or as part of an expression as shown below:primaryhierarchical_identifier [ range_expression ]range_expressionexpressionmsb _constant_expression: 1sb_constant_expressionbase_expression +: width_constant_expessionbase_expression -: width_constant_expessionIn the formal syntax, a primary is one definition of an expression; shown here is thebit- or part-select specification. The first definition of the range_expression is a bitselect, and the second is the part-select.
The last two specify a starting bit and awidth. The width is either counted up (+) or down (-) from the base expression. thusvector[23- :8]is vector[23:16]. The indices of the bit- and part-select may be positive or negativenumbers.After the initialization to determine the final arithmetic sign, the repeat statementexecutes the statements in the begin-end block 16 times. Each time, the quotient anddividend are shifted left one position, as described by the < < operator, and then thedivisor is subtracted from the top part of the dividend. If the result of this subtract ispositive, one is added to the quotient. However, if the result is negative (the top mostbit is a one), the else part of the if conditional statement is executed, adding the divisor back into the top part of the dividend.Behavioral Modeling79Following this more closely, if the sign bit is 1, then the result is negative.
Thisnonzero value would be interpreted as TRUE by the if statement. However, the ! operator complements the result and the if expression evaluates to FALSE. Thus, if the dividend is negative, the else part is executed.Finally, if the signs of the original operands are different, then the quotient isnegated. After the quotient output is calculated, the done bit is set to one signallinganother module that the output may be read.Before continuing on, this example illustrates some other facets of the languagethat should be discussed.Vector nets and registers all obey the laws of arithmetic modulo where n is thenumber of bits in the vector. In effect, the language treats the numbers as unsignedquantities. If any of these values were printed by aorstatement,they would be interpreted and printed as unsigned values.
However, that does notstop us from writing descriptions of hardware that use the two’s complement numberrepresentation — the laws of arithmetic modulo still hold. Indeed, the unary minusprovided in the language performs the correct operation. In this example, we havedeclared the registers dividend, divisor, and quotient to be signed. They will printcorrectly.The relational operators typically used in conditional expressions are listed inAppendix B. These include > (greater than), >= (greater than or equal), = = (equal),and != (not equal). In the case where unknown or high impedance values are present,these comparisons may evaluate to a quantity which contains unknown or highimpedance values. Such values are considered to be FALSE by the simulator. However,the case equality operator (= = =) and inequality operator (!= =) can be used to specifythat individual unknown or high impedance bits are to take part in the comparison.That is, a 4-valued logic comparison is done where the value of each bit being compared, including the unknowns and high impedances, must be equal.
Thus, if thestatementif(4'b110z= = =4'b110z)then_statement;was executed, the then part of the if would be taken. However, if the statementif(4'b110z==4'b110z)then_statementwas executed, the then part of the if would not be taken.The Verilog Hardware Description Language80Conditional expressions may be more complex than the single expression examplesgiven so far.
Logical expressions may be connected with the && (AND), || (OR), and !(NOT) logical operators as shown in the following example:if((a>b)&&((c>=d)||(e==f)))then_statementIn this example, the then statement will execute only if a is greater than b, and either(or both) c is greater than or equal to d, or e equals f.References: bit-select, part-select E.1;F.1;F.2; Verilog operators C3.2.1 Where Does The ELSE Belong?Example 3.1 also shows the use of an else clause with an if statement. The else clauseis optional, and if it exists, it is paired with the nearest, unfinished if statement. Formally speaking:conditional_statementif (expression) statement_or_null [ else statement_or_null ]In the example we find:if (! dividend [`DdLen-1])quotient = quotient + 1;elsedividend[`DdLen-1:`HiDdMin] =dividend[`DdLen-1:`HiDdMin] + divisor;In this case, if the dividend is positive after subtracting the divisor from it, then thelow order bit of the quotient is set to one.
Otherwise, we add the divisor back into thetop part of the dividend.As in most procedural languages, care must be taken in specifying the else clausewhere multiple if statements are involved. Consider the following situation.if (expressionA)if (expressionB)a = a + b;elseq = r + s;In this example, we have nested if statements and a single else.
In general, the language attaches the else to the nearest if statement. In the above situation, if expressionA and expressionB are both TRUE, then a is assigned a new value. If expressionABehavioral Modeling81is TRUE and expressionB is FALSE, then q is assigned a new value. That is, the else ispaired with the second if.Consider an alternate description giving different results.if (expressionA)beginif (expressionB)a = a + b;endelseq = r + s;In this example, the begin-end block in the first if statement causes the else to bepaired with the first if rather than the second. When in doubt about where the elsewill be attached, use begin-end pairs to make it clear.3.2.2 The Conditional OperatorThe conditional operator ( ?:) can be used in place of the if statement when one oftwo values is to be selected for assignment.
For instance, the statement determiningthe final sign of the quotient in Example 3.1 could have been written with the sameresult asquotient = (negDivisor != negDividend) ? -quotient: quotient;.This operator works as follows: first the conditional expression in the parentheses isevaluated. If it is TRUE (or nonzero), then the value of the right-hand side of the statement is found immediately after the question mark. If it is FALSE, the value immediately after the colon is used. The result of this statement is that one of the two valuesgets assigned to quotient. In this case, if it is TRUE that the signs are not equal, thenquotient is loaded with its negative.
Otherwise, quotient remains unchanged. As inExample 3.1, we are describing hardware that will use the two’s complement numbersystem, and we use the fact that a Verilog’s unary minus operation implements a two’scomplement negate.The general form of the conditional operator is:conditional_expressionexpression ? expression : expression|If the first expression is TRUE, then the value of the operator is the second expression.Otherwise the value is the third expression. The operator is right-associative.The Verilog Hardware Description Language82There is a major distinction between if-then-else and the conditional operator.
Asan operator, the conditional operator may appear in an expression that is either part ofa procedural or continuous assignment statement. The if-then-else construct is astatement that may appear only in the body of an initial or always statement, or in atask or function. Thus whereas if-then-else can only be used in behavioral modeling,the conditional operator can be used both in behavioral and gate level structural modeling.References: if-then-else 3.2; comparison with multiway branch 3.43.3 LoopsIterative sequential behavior is described with looping statements.
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