Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 17
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Two always blocks; one for the combinational logic and the other for thesequential.Logic Synthesis69C. Oops, this circuit is too slow. We can’t have three gate delays between the flipflop outputs and inputs; rather only two. Change part B so that Y is a combinational output, i.e. Move the gate generating d2 to the other side of the flip flops.D.
Simulate all of the above to show that they are all functionally equivalent.2.8Design, implement, and simulate a 4-bit two’s complement adder/subtractorcircuit to compute (A+B), (A-B), sat(A+B), or sat(A-B) when a two-bit add_selbit is 00, 01, 10, or 11, respectively. sat(x) is saturating addition. Saturatingarithmetic is analogous to other kinds of saturation — numbers can only get sobig (or so small) and no bigger (or smaller), but they don’t wrap, unlike in modulo arithmetic.For example, for a three-bit saturating adder, 010 + 001 = 011 (2+1=3, OK,fine), but 011 + 001 = 011 (3+1=3, huh?), i.e, instead of “wrapping” to obtain anegative result, let’s just represent the result as close as we can, given our limitednumber of bits.Similarly for negative results, 111+101 = 100 (-1+(-3) = -4), but 100 + 111 = 100(-4 + (-1) = -4, i.e, the smallest, or most negative representation in 3-bit, two’scomplement).Assume complemented inputs for B are not available.
Write your descriptionentirely in a synthesizable procedural Verilog style. Simulate and show enoughtest cases to verify your design (that does not mean all possible input cases thistime!).The Verilog Hardware Description Language702.9 Consider the statetransition diagramshown to the right.The output of theFSM is three bits,but states A and Conly use two bits forthe output.
For eachof the followingencodingstyles,(binaryencoding,output encoding, onehot encoding:):A. Show the state assignmentB. Derive boolean equations for the next state logic and output logic in minimized SOP. Show all your work and reasoning for full credit.C. Design (draw) the circuit using positive edge-triggered D flip-flops withnegative-logic preset and reset signals. Show the reset logic of the FSM.D. Write a synthesizable Verilog simulation of your design.
Write a test moduleto test your module with input sequence (read left to right) 11010001100. Usedecimal format for the FSM outputs. Hand in the source code and output.2.10 For the Mealyfinitestatemachine shown tothe right,A. Write a proceduralVerilogimplementationfor your mealymachine.B. Simulate andtest your circuitforaninputsequence (read leftto right) of 100101101111. Display the output sequence of your machine indecimal (i.e., 0,1,2,3) and relate it back to your input sequence.
Your simulationLogic Synthesis71results must show that your machine behaves like a Mealy machine. In a Mealy,if you change inputs between block events, the output should follow, no matterhow many times you change the inputs. Your simulation results must show this!2.11 Design a Mealy finite state machine with one input, X, and one output,Y. Withthis state machine, you get an output of Y=1 every time the input sequence hasexactly two or exactly four 1’s in a row.
Y=0 otherwise. Make sure your machinedoes this:Input: 0110111011110111110Output:0001000000001000000Notice how you can’t tell if you get exactly two or exactly four 1’s until you see thenext input. It sort of makes the timing look like a Moore machine, but it isn’t.It’s a Mealy.
And you must design the machine as a Mealy! Write a Verilogimplementation for your mealy machine. Simulate and test your circuit usingthe input sequence given above.3BehavioralModelingWe now begin a more in-depth discussion of the constructs used to model the behavior of digital systems. These have been split into two groups. The first are statementsthat are, for the most part, similar to those found in programming languages: if-thenelse, loops, etc.
In the next chapter we take up the statements that are oriented towardmodeling the concurrent nature of digital hardware.3.1 Process ModelThe basic essence of a behavioral model is the process. A process can be thought of asan independent thread of control, which may be quite simple, involving only onerepeated action, or very complex. It might be implemented as a sequential statemachine, as an asynchronous clearing of a register, or as a combinational circuit. Thepoint is that we conceive the behavior of digital systems as a set of these independent,but communicating, processes.
Their actual implementation is left to the context ofthe description (what level of abstraction we are dealing with) and the time and areaconstraints of the implementation.The Verilog Hardware Description Language74The basic Verilog statement for describing a process is the always construct:always_constructalways statementThe always continuously repeats its statement, never exiting or stopping. A behavioralmodel may contain one or more always statements. If a module contains none, it ispurely a specification of hierarchical structure — instantiated submodules and theirinterconnections.The initial construct is similar to the always statement except that it is executedonly once.initial_constructinitial statementThe initial provides a means of initiating input waveforms and initializing simulationvariables before the actual description begins simulation.
Once the statements in theinitial are executed it does not repeat; rather it becomes inactive.There are many types of procedural statements in the language. Some, such as “if”,“while”, and procedural assignments have already been seen in earlier examples. Theseand most of the rest of the statement types will be covered in the next two chapters.When modeling a system using the statements in an always or initial block, wemust be cognizant of the execution model of these statements.
The statements areexecuted in the order specified in the description. Assignments made using the blocking assignment (“=”) take effect immediately and the value written to the left-hand sideof the = is available for use in the next statement. When an event statement (“@”), adelay statement (“#”), or, as we’ll see later, a wait statement where the expression isFALSE is executed, the execution of the initial or always statement is suspended until(respectively): the event occurs, the number of time units indicated in the delay haspassed, or the wait statement expression becomes TRUE. At that time, execution ofstatements in the initial or always statement continues.Further, even though the statements in an always or initial block are executed inorder, it is possible that statements from other always or initial blocks will be interleaved with them. When an always or initial block is waiting to continue (due to @, #,or wait), other always or initial blocks, gate primitives, and continuous assign statements can execute.
Thus, concurrent/overlapping behavior is modeled.Unlike gate primitives and continuous assign statements, behavioral models do notexecute because one of their inputs change. Rather, they only execute when one of thethree conditions above is being waited for, and then occurs. Behavioral models followthe procedural timing model as discussed in Section 8.1.Behavioral Modeling75At the start of the simulation, all of the initial and always statements are allowed toexecute until they are suspended due to an event, delay, or wait. At this point, registervalues set in an initial or always may activate a gate input, or time may advance to thenext event that will probably allow one or more of the suspended processes to becomeactive again.
When there are multiple processes that can execute at any particulartime, the order in which they begin executing is arbitrary. Care must be taken whenwriting them to insure that register and wire values are assigned in an appropriateorder.In summary, the initial and always statements are the basic constructs for describing concurrency.
When using these statements, we should be thinking conceptually ofconcurrently active processes that will interact with each other. Although it is possibleto mix the description of behavior between the always and initial statement, it is moreappropriate to describe the behavior of the hardware in the always, and describe initialization for the simulation in the initial.References: contrast to continuous assign 6.3; contrast to gate level modeling 6.1; interleaving 8.3; procedural timing model 8.13.2 If-Then-ElseConditional statements are used in a sequential behavior description to alter the flowof control.
The if statement and its variations are common examples of conditionalstatements. Example 3.1 is a behavioral model of a divide module that shows severalnew features, including two versions of the if statement, with and without an elseclause.The divide module determines the output quotient from the two inputs, dvInputand ddInput, using an iterative subtract and shift algorithm. First, four text macrosare defined. The `define compiler directive provides a macro capability by defining aname and gives a constant textual value to it. The name may then be used in thedescription; on compilation, the text value will be substituted. The general form is:`define A alphaThen, anytime the description is compiled, alpha will be substituted for all occurrences of “ `A ”.
Note that the left single quote (“ ` ”) is required at all uses of themacro. Example 3.1 illustrates a means of entering constant numeric data into thedescription using the more mnemonic macro.The Verilog Hardware Description Language76`defineDvLen 16`define DdLen 32`define16`define HiDdMin 16module divide(inputoutput reg signedinputoutput regregregregsignedsigned[`DdLen-1:0][`DdLen-1:0][`DvLen-1:0]ddInput, dvInput,quotient,go,done);dividend;divisor;negDivisor, negDividend;always begindone = 0;wait (go);divisor = dvInput;dividend = ddInput;quotient = 0;if (divisor) beginnegDivisor = divisor[`DvLen-1];if (negDivisor)divisor = - divisor;negDividend = dividend[`DdLen-1];if (negDividend) dividend = - dividend;repeat (`DvLen) beginquotient = quotient << 1;dividend = dividend << 1;dividend[`DdLen-1:`HiDdMin] =dividend[`DdLen-1:`HiDdMin] - divisor;if (! dividend [`DdLen-1]) quotient = quotient + 1;elsedividend[`DdLen-1:`HiDdMin] =dividend[`DdLen-1:`HiDdMin] + divisor;endif (negDivisor != negDividend) quotient = - quotient;enddone = 1;wait (~go);endendmoduleExample 3.1 A Divide ModuleBehavioral Modeling77The divide starts by zeroing the done output and waiting for go to be TRUE.
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