Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 12
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Assigningto the combinational output in every control path will insure this.An example of a module synInferredLatchsituation that infers a(output reg f,latch is shown ininputa, b, c);Example 2.7. If wefollow the controlalways @(*)paths in this examif (a == 1)ple, we see that if a isf = b & c;equal to one, then f is endmoduleassigned the value ofb & c. However, if aExample 2.7 An Inferred Latchis equal to zero, then fis not assigned to inthe execution of the always block. Thus, there is a control path in which f is notassigned to. In this case a latch is inferred and the circuit shown on the right of theexample is synthesized.
The latch is actually a gated latch — a level-sensitive deviceLogic Synthesis43that passes the value on its input D when the latch’s gate input (G which is connectedto a) is one, and holds the value when the latch’s gate input is zero.2.3.3 Using Case StatementsExample 2.8 illustrates using a case statement to specify a combinational function ina truth table form.
(This example specifiesthe same logic function as Examples 2.1and 2.2.) The example illustrates and follows the rules for specifying combinationallogic using procedural statements: all members of the always’ input set are containedin the always’ sensitivity list — the @(*)insures this, the combinational output isassigned to in every control path, and thereare no edge specifications in the sensitivitylist.module synCase(output reg f,inputa, b, c);always @(*)case ({a, b, c})3'b000:3'b00l:3'b0l0:3'b011:3'b100:3'bl0l:3'b110:3'b111:endcaseendmodulef = 1'b0;f = 1'b1;f = 1'b1;f = 1'b1;f = 1'b1;f = 1'b0;f = 1'b0;f = 1'b1;The first line of the case specifies theconcatenation of inputs a, b, and c as themeans to select a case item to execute. Theline following the case keyword specifies a Example 2.8 Combinational LogicSpecified With a Case Statementnumeric value followed by a colon.
Thenumber 3'b000 is the Verilog notation for a3-bit number, specified here in binary as 000. The b indicates binary. The right-handsides of the assignments to f need not be constants. Other expressions may be usedthat include other names. The @(*) will include them in the sensitivity list.Of course, when using a case statementit is possible to incompletely specify thecase. If there are n bits in the case’s controlling expression, then a synthesis toolwill know that there arepossible control paths through the case. If not all ofthem are specified, then there will be acontrol path in which the output is notassigned to; a latch will be inferred.
Thedefault case item can be used to define theremaining unspecified case items. ThusExample 2.8 could also be written asshown in Example 2.9. Here, we explicitlylist all of the zeros of the function usingmodule synCaseWithDefault(output reg f,inputa, b, c);always @(a, b, c)case ({a, b, c})3'b000:3'b101:3'b110:default:endcaseendmodulef = 1'b0;f = 1'b0;f = 1'b0;f = 1'b1;Example 2.9 Using Default to FullySpecify a Case Statement44The Verilog Hardware Description Languageseparate case items. If the input does not match one of these items, then by default f isassigned the value one.References: case 3.4, numbers B.3.2.3.4 Specifying Don’t Care SituationsLogic synthesis tools module synCaseWithDCmake great use of logi(output reg f,cal don’t care situationsinputa, b, c);to optimize a logic circuit.Example 2.10always @(*)illustrates specifying acase ({a, b, c})logic function that con3'b001: f = 1'b1;tains a don’t care.
Often3'b010: f = 1'b1;these can be specified in3'b011: f = 1'b1;the default statement of3'b100: f = 1'b1;a case. As shown,3'b110: f = 1'b0;assigning the value x to3'b111: f = 1'b1;the output is interdefault: f = 1'bx;preted in this exampleendcaseas specifying input cases endmodule3'b000 and 3'b101 to bedon’t cares. An opti- Example 2.10 A Logic Function With a Don’t Caremized implementationof this function isshown on the right; only the single zero of the function (input case 3'b110) is implemented and inverted.
In general, specifying an input to be x allows the synthesis toolto treat it as a logic don’t care specification.Two attributes are often used to help synthesis tools optimize a function. These arethe full_case and parallel_case attributes illustrated in Example 2.11. The case statement in Example 2.10 is full by definition because all of the case items are specifiedeither explicitly or by using a default.
Thus all of the control paths are also specified.Synthesis tools look for the full_case attribute specified on a case statement indicatingthat the case is to be considered full even though all case items are not specified. Inthis situation, the unspecified cases are considered to be don’t cares for synthesis, anda latch is not inferred.Logic Synthesis45An attribute is specified as shown on line6 of Example 2.11. Attributes are declaredas a prefix to the statement to which theyrefer; in this situation it is on the line beforethe case statement it refers to. (Attributesare not comments, nor are their namesdefined by the language.
Rather, other toolsthat use the language, such as a synthesistool, define their names and meanings.Consult their user manuals for details andexamples of usage.)module synAttributes(output reg f,inputa, b, c);always @(*)(* full_case, parallel_case *)case ({a, b, c})3'b001: f = 1'b1;3'b010: f = 1'b1;3'b011: f = 1'b1;3'b100: f = 1'b1;3'b110: f = 1'b0;3'b111: f = 1'b1;endcaseendmoduleAlso shown in the example is a parallelcase attribute.
A Verilog case statement isallowed to have overlapping case items. Inthis situation, the statements for the matching items are executed in the order speciExample 2.11 Case Attributesfied. This can result in some complex logicbecause a priority among the case items isspecified. A parallel case is a case statement where there is no overlap among the caseitems. That is, only one of the case items can be true at any time. If the case is parallel(and full), it can be regarded as a sum-of-products specification which could be implemented by a multiplexor.
Specifying the parallel case attribute enables this interpretation and generally simplifies the logic generated.A casex statement,which allows for the useof x, z, or ? in the controlling expression or ina case-item expression,can be used for specifying don’t cares for synthesis. However, x, z, or? may only be specifiedin a case item expression for synthesis.module synUsingDC(output reg f,inputa, b);always @ (*)casex ({a, b})2'b0?: f = 1 ;2'b10: f = 0 ;2'b11: f = 1 ;endcaseendmoduleConsider the mod- Example 2.12 Specifying a Logical Function Using auleshowninExample 2.12.
The first case item specifies that if a is zero, then the output f is one.The use of the ? in this statement specifies that the value of b does not matter in thissituation. Thus this case item covers the first column of the Karnough map. Althoughwe could have specified the two case items (2'b00 and 2'b01) and assigned f to be x inboth situations, the approach shown is more compact.
Since this first case item covers46The Verilog Hardware Description Languagetwo of the four possible case-items, it along with the other two case-items make this afull casex.When using the ? in thecase-item expressions, thecase items can overlap.Example 2.13 illustrates howa one-hot state assignmentcould lead to overlappingcase items.
Specify the casewiththefullandparallel_case attributes; thesynthesizer will then treateach case as exclusive andgenerate more optimizedlogic.module oneHotEncoding(output reg [2:0] state,inputin, ck);always @(posedge ck)(* full_case, parallel_case *)casex (state)3'b1??: state <= 3'b010;3'b?1?: state <= in ? 3'b010: 3'b001;3'b??1: state <= in ? 3'b100: 3'b001;endcaseendmoduleExample 2.13 Use of Full and Parallel CaseThe casez statement canalso be used to specify logicaldon’t cares.
In this situation, only z or ? are used for the don’t care in the case-itemexpression.Care should be taken when using don’t cares in a specification because they giverise to differences between simulation and synthesis. In a simulator, an x is one of thefour defined logic values that will be printed when tracing values. However, in thesynthesized circuit, the value printed for the same situation will either be 1 or 0. Further, comparing to an x makes sense in a simulation but not in synthesis. To reducethe differences between simulation and synthesis, a synthesizable description does notcompare with x or z.References: casex and casez 3.4.2.3.5 Procedural Loop ConstructsA reading of the above examples might suggest that the only means to specify logicfunctions is through if and case statements. The for loop in Verilog may be used tospecify combinational logic.
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