Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 11
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In a simulation of the circuit, theresult of the logical expression on the right-hand side of the equal sign is evaluatedanytime one of its values changes and the result drives the output f.In this example, the same sum of products functionality from Example 2.1 is usedbut the assign statement is written combining products 1, 2, and 3 into the last product term. Of note is the fact that a continuous assign may call a function which contains procedural assignment statements. The use of procedural assignment statementsto describe combinational logic will be discussed in section 2.3; thus we will limit thediscussion here to continuous assigns without function calls.Logic Synthesis39Continuous assign statementsmodule addWithAssignare often used for describing#(parameter WIDTH = 4)datapath elements.
These mod(outputcarry,ules tend to have one-line specioutput [WIDTH-1:0]sum,fications as compared to the logicinput [WIDTH-1:0]A,B,specifications for next state andinputCin);output logic in a finite statemachine. In Example 2.3 bothassign {carry, sum} = A + B + Cin;an adder and a multiplexor areendmoduledescribedwithcontinuousassign. TheaddWithAssignmodule muxWithAssignmodule is parameterized with#(parameter WIDTH = 4)the width of the words being(output [WIDTH-1:0] out,added and include carry in (Cin)input[WIDTH-1:0] A, B,and carry out (carry) ports.
Noteinputsel);that the sum generated on theright-hand side of the assignassign out = (sel) ? A: B;generates a result larger thanendmoduleoutput sum. The concatenationoperator specifies that the topExample 2.3 Datapath Elements Describedmost bit (the carry out) will driveWith Continuous Assignthe carry output and the rest ofthe bits will drive the sum output. The multiplexor is described using the conditional operator.There are limits on the operators that may be used as well as the ways in whichunknowns (x) are used. An unknown may be used in a synthesizable description butonly in certain situations. The following fragment is not synthesizable because it compares a value to an unknown.assigny = (a === 1'bx)? c : 1 ;An unknown used in this manner is a value in a simulator; it is useful in determiningif the value of a has become unknown.
But we do not build digital hardware to compare with unknowns and thus this construct is not synthesizable. However, the following fragment, using an unknown in a non-comparison fashion, is allowable:assign y = (a == b) ? 1'bx : c ;In this case, we are specifying a don’t-care situation to the logic synthesizer. That is,when a equals b, we don’t care what value is assigned to y. If they are not equal, thevalue c is assigned. In the hardware synthesized from this assign statement, either 1 or0 will be assigned to y (after all, there are no unknowns in real hardware). A don’t-carespecification used in this manner allows the synthesizer additional freedom in optimizing a logic circuit. The best implementation of this specification is just y = c.40The Verilog Hardware Description LanguageReferences: assign 6.3; primitive gates 6.2; parameters 5.2.2.3 Procedural Statements to SpecifyCombinational LogicIn addition to using continuous assign statements and primitive gate instantiations tospecify combinational logic, procedural statements may be used.
The procedural statements are specified in an always statement, within a task called from an always statement, or within a function called from an always statement or a continuous assign. Inspite of the fact that a description using procedural statements appears sequential,combinational logic may be specified with them. Section 1.2 introduced this approachto specifying combinational logic. This section covers the topic in more detail.2.3.1 The BasicsThe basic form of a procedural description of combinational logic is shown inExample 2.4.
It includes an always statement with an event statement containingall of the input variables to the combinational function. The example shows amultiplexor described procedurally. Inthis case, input a selects between passinginputs b or c to output f. Even though f isdefined to be a register, a synthesis toolwill treat this module as a specification ofcombinational logic.module synCombinationalAlways(output reg f,inputa, b, c);always @ (a, b, c)if (a == 1)f = b;elsef = c;endmoduleExample 2.4 Combinational LogicDescribed With Procedural StatementsA few definitions will clarify the ruleson how to read and write such descriptions.
Let’s define the input set of the alwaysblock to be the set of all registers, wires, and inputs used on the right-hand side of theprocedural statements in the always block. In Example 2.4, the input set contains a, b,and c. Further, let’s define the sensitivity list of an always block to be the list of namesappearing in the event statement (“@”). In this example, the sensitivity list contains a,b, and c. When describing combinational logic using procedural statements, everyelement of the always block’s input set must appear without any edge specifiers (e.g.,posedge) in the sensitivity list of the event statement. This follows from the verydefinition of combinational logic — any change of any input value may have animmediate effect on the resulting output.
If an element of the input set is not in thesensitivity list, or only one edge-change is specified, then it cannot have an immediateeffect. Rather, it must always wait for some other input to change; this is not true ofcombinational circuits.Logic Synthesis41Considering Example 2.4 further, we note that the combinational output f isassigned in every branch of the always block.
A control path is defined to be a sequenceof operations performed when executing an always loop. There may be many differentcontrol paths in an always block due to the fact that conditional statements (e.g. caseand if) may be used. The output of the combinational function must be assigned ineach and every one of the possible control paths. Thus, for every conceivable inputchange, the combinational output will be calculated anew; this is a characteristic ofcombinational logic.The above example and discussion essentially outline the rules for specifying combinational hardware using procedural statements: the sensitivity list must be the inputset and contain no edge-sensitive specifiers, and the combinational output(s) must beassigned to in every control path.A common error in specifying combinational circuits with procedural statements is to incorrectly specify thesensitivity list.
Example 2.4 is revised touse the @(*) construct as shown inExample 2.5 — the two examples willsimulate and synthesize identically.Essentially, @(*) is shorthand for “all thesignals on the right-hand side of thestatement or in a conditional expression.”always @ (*)if (a == 1)f = b;elsef = c;endmoduleThe basic form of the “@” event statement is:Example 2.5 AutomaticallyDetermining the Sensitivity Listmodule synAutoSensitivity(output reg f,inputa, b, c);@ (sensitivity_list) statement;When using the construct @(*) — or @* which is equivalent — only the statement’sright-hand side or conditional expression is included. Thus, if several proceduralstatements are needed to specify the combinational function, a begin-end block mustbe used to group them into a compound statement. The “@(*) begin-end” will theninclude the registers and nets from the right-hand sides and conditionals of all of thestatements in the compound statement.42Although this relieves the problem ofcorrectly specifying the sensitivity list forcombinational functions, the rule concerning assigning to the combinationaloutput(s) during any execution of thealways block must still be followed.
Anapproach to organizing descriptions sothat an assignment is always made isshown in Example 2.6. This module hasthe same multiplexor functionality asExample 2.5. However, here the output fis assigned to first. In a complex description, this approach ensures that a latchwill not be inferred because of a forgottenoutput assignment.The Verilog Hardware Description Languagemodule synAssignOutputFirst(output reg f,inputa, b, c);always @ (*) beginf = c;if (a == 1)f = b;endendmoduleExample 2.6 AutomaticallyDetermining the Sensitivity ListReferences: always 3.1; sensitivity list 8.1; @ 4.2; edge specifications 4.2; input set 7.2.1, functions andtasks 3.5.2.3.2 Complications — Inferred LatchesIf there exists a control path that does not assign to the output, then the previous output value needs to be remembered.
This is not a characteristic of combinational hardware. Rather it is indicative of a sequential system where the previous state isremembered in a latch and gated to the output when the inputs specify this controlpath. A logic synthesis tool will recognize this situation and infer that a latch isneeded in the circuit. Assuming that we are trying to describe combinational hardware, we want to insure that this inferred latch is not added to our design.
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