Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 9
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The complete formal syntax specification is inAppendix G.The rest of the book illustrates in more depth the syntax and semantics of the Verilog language.1.6 ExercisesFor more exercises, see Appendix A.1.11.21.31.41.51.6Rewrite the eSeg module in Example 1.4 with continuous assignment statements.Write three different descriptions of a 2-bit full adder including carry-in andcarry-out ports. One description should use gate-level models, another shoulduse continuous assignment statements, and the third — combinational always.Change the clock generator m555 in Example 1.9 such that the clock periodremains the same but that the low pulse width is 40 and high pulse width is 60.Write a two-phase clock generator.
Phase two should be offset from phase oneby one quarter of a cycle.Keeping the same output timing, replace the initial and always statements in theclock generator m555 in Example 1.9 with gate primitives.Write a behavioral description for a serial adder. The module definition is:module serialAdder (input clock, a, b, start,output sum);endmoduleA.
The bits will come in to the module low order first. The carry into the loworder bits is assumed to be zero. The inputs are all valid right before the negativeedge of the clock. a and b are the two bits to add and sum is the result. If start is1, then these two bits are the first of the word’s bits to add. Just after the negative edge of the clock, sum will be updated with its new value based on the values of a and b (and the carry from the previous bits) just before the clock edge.B. Create a test module to demonstrate the serial adder’s correctness.Verilog — A Tutorial Introduction1.7Oops, forgot the declarations! Here’s a Verilog module that is complete exceptfor the register, input, and output declarations. What should they be? Assume a,b, and c are 8 bit “things” and the others are single-bit.
Note that you may haveto add to the input-output list. Do not add any more assignments — only input,output, and register declarations.module sillyMe (a, b, c, q,…);// oops, forgot the declarations!initialq = 1’b0;alwaysbegin@ (posedge y)#10 a = b + c;q = ~q;endnand#10endmodule1.829(y, q, r);Spock claims that he cantranslate K-maps with fourvariables or less directlyinto accurate Verilog module descriptions. He takesone glance at the K-map onthe right and produces theVerilog module the_ckt.The Verilog Hardware Description Language30module the_ckt(output f,input a, b, c, d);(f3, f1, d),(f4, f2, b);xnor (f1, a, c);not(f2, f1);or(f, f3, f4);endmoduleandA.
Write a test module, called verify_spock that allows you to determinewhether the Verilog description matches the K-map. Write a top module, calledtop_spock to wire your test module to the the_ckt module. The output of theexecution of your simulation module must relate easily to a truth table description of the function and the minterms represented on the K-map.
Use a for loopto generate the test values in your testbench.1.9The all-nand circuit below is intended to implement the function, F=X xor Y.However, it produces a glitch (a temporarily incorrect output) under certainkinds of changes in the set of signals applied to the inputs.module weird_xor(outputxor_out,inputx,y);nand #3g1(f1,x,y),g3(f3,f1,y);nand#lg2(f2,x,f1),g4(xor_out, f2, f3);endmoduleWrite a complete simulation that will show when a glitch happens. Make a testmodule, weird_xor_test that provides sets of test inputs and a system module,weird_xor_system, that instantiates both of the other modules and wires themtogether. Explain exactly how a glitch is detected by your simulation results.1.10 Consider the description below:Verilog — A Tutorial Introduction31module bad_timing(output f_out,input a, b, c);nand #10gl(f1,a,b),g2(f_out,f1,c);endmoduleA.
Draw the circuit described by the module. Completely label all signals andgates, including propagation delays.B. This circuit will output a glitch (a temporarily incorrect output) under certain operating conditions. Describe the circumstances that cause a glitch in thiscircuit.C. Write a complete simulation that will show when a glitch happens. Make atest module, bad_timing_test that provides sets of test inputs and a systemmodule, bad_timing_system, that instantiates both of the other modules andwires them together.D. Explain exactly how a glitch is detected by your simulation results.E. Draw a timing diagram to illustrate the glitch modeled in your simulation.1.11 Consider the Verilog description below.module what_is_it(output f_outinput x,y);nand #10g1(f1,x,x),g2(f2,y,y),g3(f3,x,y),g4(f4,f1,f2),g5(f_out,f3,f4);endmoduleA. Draw the circuit described by the Description.
Completely label all signalsand gates, including propagation delays.B. The what_is_it module can be replaced with another primitive gate in Verilog. What is the primitive gate?321.12The Verilog Hardware Description LanguageA great philosopher said, “A man is satisfied when he has either money, poweror fame. However, all these mean nothing to him if he is going to die.”A. Design a Verilog module from the word problem that implements a Satisfaction Detector with inputs Has_Money, Has_Power, Has_Fame,Going_To_Die and output Has_Satisfaction.
Use whatever gates you want, solong as your description implements the problem statement. Call the moduleSatisfaction_Detector.As it turns out, this philosopher designed, developed, and marketed his Satisfaction Detector but the manufacturing technology caused the detector to failafter anywhere from 10-100 uses. He became famous for marketing defectivemerchandise. Thus he is famous, but he is not satisfied.
Back to the drawingboard:You have been hired to help this man to build a revised Satisfaction Detector.The new Satisfaction Detector still has inputs Has_Money, Has_Power,Has_Fame, Going_To_Die and output Has_Satisfaction. Only this time, addanother input called, Keeps_on_Trying. In addition to the logic of the old Satisfaction Detector, where any of money, power or fame will indicate satisfaction,the new Satisfaction Detector will also indicate satisfaction if the man keeps ontrying, no matter what else (even if he is dying)!B. Use the Satisfaction_Detector module designed in part A as the core ofyour new design.
Build another module, Satisfaction_Detector_II whichincludes the logic for new input, Keeps_on_Trying. Be sure to use the moduleyou designed for part A!C. Simulate your Satisfaction_Detector_II module. Include enough test casesin your testbench to determine if your new detector is working correctly.1.13Implement the following in structural Verilog. Much publicity was given to thewomen’s US Soccer team for winning the title several years back — and for oneof the player’s removing her jersey after the big win. Someone collected a lot ofopinions and came up with the following set of rules for when it’s OK to removeone’s jersey on the field after a game.
We’ll call the output of the rule implementor Jersey_Freeway which is asserted if it’s OK for a player to take off her Jerseyafter a game. The logic works like this. If a player scored the winning goal(Winning_Goal) or was the goalie (Goalie) and her team won the game(Won), then she can take off her jersey (Jersey_Freeway), but only if she didnot become bruised during the game (Bruised).A. Design a Verilog Module called Jersey_Freeway to implement an all-NANDdesign of the logic.Verilog — A Tutorial Introduction33B. Simulate your design and verify that your implementation satisfied the worddescription. How will you do the verification?C.
Alas, the rules have now been extended. The circuit must be modified. Aplayer should never remove her jersey unless her team won the game, except ifthis is her last game (Retiring) when she always should, unless she is too badlybruised by the game. Design a Verilog module for a new Jersey_Freeway detector, called New_Jersey_Freeway to implement the design with this additionalrule.
Don’t re-design from scratch! Re-use your Jersey_Freeway module in thedesign of your New_Jersey_Freeway detector. The solution must have one module containing another module.D. Simulate and verify your design of part C.1.14Implement the following in structural Verilog. As with most things, Engineersare way ahead of the general public. For instance, we’ve had our own version ofSurvivor for years. In fact, some folks have derived logic for this. The logic forHW_Design_Survivor works like this.
If a designer’s partner packs a rat intheir backpack for those long design sessions (rat is asserted) and forms an alliance with a group of designers who do not use VHDL (non_VHDL_alliance isasserted) they will survive. Or if a designer passes both immunity hardware testchallenges (immunity1 and immunity2 are asserted) and does not show up tothe final presentation naked (naked is most definitely de-asserted), they will alsobe a hardware design survivor.
Assume complemented inputs are available.A. Design an all-NAND implementation which uses a minimal number of gates.Show all work, including how you arrived at a minimal design. Actually draw allgates for this part.B. Design a Verilog module called survivor to implement part A.C. Simulate your design and verify that your implementation satisfied the worddescription. How will you do the verification?D. Now we are going to extend the rules for survival.
A designer will survive ifthey always follow the rules for synthesizable hardware (synthesis is asserted)and never try to gate the clock (gate is de-asserted), regardless of anything else.Design a second Verilog module for a modified survivor logic box, calledsurvivor_II to implement the design with this additional rule. Only don’t redesign from scratch, re-use your previous design in the design of yourSurvivor_II detector.
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