Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 4
Текст из файла (страница 4)
However, the simulator can only update them one at a time. All we know about the orderof updates is that it will be arbitrary — we cannot assume that one will happen beforethe other.The result of propagating these four new values on wires p1, p2, p3, and p4, is thatgate g5 will be scheduled to change its output value at time 12. Since there are no further events during the current time (11), the next event is taken from the event list atthe next time, which is 12. The change to eSeg at time 12 will not cause any othergates to be evaluated because it is not connected to any other gates.The simulation continues until the initial statement executes the finish command.Specifically, at time 20, D is set to 1.
This will cause a change to eSeg two time unitslater. Then at time 30, D is set to 0, C is set to 1, and eSeg changes its output twotime units later. At time 40, thecommand stops the simulation program.The simulator output in Figure 1.1 illustrates three of the four values that a bit mayhave in the simulator: 1 (TRUE), 0 (FALSE), and x (unknown). The fourth value, z, isused to model the high impedance outputs of tristate gates.We now can see why A, B, C, and D were defined as registers for the examples ofthis section. As the only “external” inputs to the NAND gates, we needed a means ofsetting and holding their value during the simulation. Since wires do not hold values— they merely transmit values from outputs to inputs — a register was used to holdthe input values.Verilog — A Tutorial Introduction7It is useful to note that we have seen the use of the two main data types in the language: nets and registers.
Primitive gates are used to drive values onto nets; initialstatements (and, as we’ll later see, always statements) are used to make assignments tothe registers.As a final comment on the simulation of this example, note that simulation timeshave been described in terms of “time units.” A Verilog description is written withtime delays specified as we have shown above. The timescale compiler directive is thenused to attach units and a precision (for rounding) to these numbers. The examples inthe book will not specify the actual time units.References: logic values 6.2.2; timescale compiler directive 6.5.3Tutorial: See the Tutorial Problems in Appendix A.1.1.1.3 Creating Ports For the ModuleOur previous binaryToESeg example had neitherinputs nor outputs — arather limiting situationthat does not representreal modules nor help indeveloping a modulehierarchy. This exampleextends our notion ofdefining modules toinclude ones that haveports.module binaryToESeg(output eSeg,input A, B, C, D);nand #1g1 (p1, C, ~D),g2 (p2, A, B),g3 (p3, ~B, ~D),g4 (p4, A, C),g5 (eSeg, p1, p2, p3, p4);endmoduleExample 1.3 Adding Ports to a ModuleThe first line is theopening module definition statement, using the module keyword and the module’sname.
On the second line, the opening parenthesis indicates that ports will bedeclared as part of this module. The ports are declared within the parenthesis to beinputs, outputs, or bidirectional inouts. Note that output(s) need not be first, as is thecase with the primitive NAND gates.
On the second line, this example declares eSeg tobe an output port. On the third line, four input ports named A, B, C, and D aredeclared. The closing parenthesis on the third line ends the declaration of the moduleports. In contrast to Example 1.2, A, B, C, and D are now wires that connect theinput ports to the gates. The binarytoESeg module might be drawn in a logic diagram as shown on the right of the example.
Note that the port names are shown onthe inside of the module in the logic diagram. The port names are only known insidethe module.8The Verilog Hardware Description LanguageThis module may now be instantiated into other modules. The port list in themodule definition establishes a contract between the internal workings of the moduleand its external usage. That is, there is one output and four inputs to connect to. Noother connections within the module (say, wire p1) can be connected outside of thismodule. Indeed, the internal structure of the module is not known from the outside— it could be implemented with NOR gates.
Thus, once defined, the module is ablackbox that we can instantiate and connect into the design many times. But sincewe don’t have to be bothered with the internal details of the module each time it isinstantiated, we can control the descriptive complexity of the design.One final note on Example 1.3. We no longer declare that eSeg, p1, p2, p3, p4 arewires. (Previously in Example 1.2, we optionally chose to declare them as wires.) Sincegates only drive nets, these names, by default, are implicitly declared to be wires.1.1.4 Creating a Testbench For a ModuleNormally in this book, we will show individual modules that illustrate specific features of the language. This works well given the space we have to present the material.However, when writing Verilog descriptions, it is often appropriate to organize yourdescription using the testbench approach.
The idea is based on a vague analogy to anengineer’s workbench where you have the system being designed wired to a test generator that is going to provide inputs at controlled time intervals and monitor the outputs as they change. In Verilog, a module is defined and, possibly, given the nametestBench. Within this module are two other modules, one representing the systembeing designed, and the other representing the test generator and monitor. These areshown in Figure 1.2.This is a clean way to separate the design’s description and the means of testing it.The system being designed, shown on the right, can be simulated and monitoredthrough its ports, and later the design might be synthesized using other CAD tools.The point is that the descriptions being simulated and synthesized are the same.
Further, all testing activity is encapsulated in the module on the left. If you includeVerilog — A Tutorial Introduction9behavior to test a design within the design’s module, then when you synthesize, youmay need to remove this behavior — an error prone process. The binaryToESegSimmodule of Example 1.2 showed a module where the design’s description (the NANDgate instantiations) and the test behavior (the initial statement) were combined.Example 1.4 shows this description rewritten using the testbench approach.module testBench;wire w1, w2, w3, w4, w5;binaryToESegtest_bToESegendmoduled (w1, w2, w3, w4, w5);t (w1, w2, w3, w4, w5);module binaryToESeg(input A, B, C, D,output eSeg);nand #1g1 (p1, C, ~D),g2 (p2, A, B),g3 (p3, ~B, ~D),g4 (p4, A, C),g5 (eSeg, p1, p2, p3, p4);endmodulemodule test_bToESeg(output reg A, B, C, D,inputeSeg);initial// two slashes introduce a single line commentbegin"A = %b B = %b C = %b D = %b, eSeg = %b",A, B, C, D, eSeg);//waveform for simulating the nand ftip ftop#10 A = 0; B = 0; C = 0; D = 0;#10 D = 1;#10 C = 1; D = 0;#10endendmoduleExample 1.4 Using the Testbench Approach to Description10The Verilog Hardware Description LanguageModule testBench instantiates two modules: the design module binaryToESegand the test module test_bToESeg.
When modules are instantiated, as shown onlines four and five, they are given names. The fourth line states that a module of typebinaryToESeg is instantiated in this module and given the name d. The fifth lineinstantiates the test_bToESeg module with name t. Now it is clear what the functionality of the system is (it’s a binary to seven segment decoder) and what its portsare.
Further, it is clear how the system is going to be tested (it’s all in the test module).The testbench approach separates this information, clarifying the description, andmaking it easier to follow on to other design tools such as logic synthesis. The connection of these two modules is illustrated in Figure 1.3.Wires need to be declared when connecting modules together. Here, wires w1through w5, declared on line two of the example, specify the interconnection. We cansee that output register A in module test_bToESeg is connected to an output of themodule. The ports are specified and connected in order. In module testBench, A isthe second port (eSeg is the first) and is connected to wire w2 (the second port in thelist of ports), which is also connected to port A on module binaryToESeg.
Insidemodule binaryToESeg, that port is connected to gates g2 and g4. Thus register Adrives the inputs of g2 and g4. Simulating module testBench will produce the sameresults as simulating module binaryToESegSim in Example 1.2.Within module test_bToESeg we have declared A, B, C, and D to be registers.This is necessary because they are being assigned to in the initial block. Assignmentsin initial and always blocks must be to registers.You might think that register A in module test_bToESeg and input net A in module binaryToESeg are the same because they are named the same.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
