Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 6
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This is a fundamental characteristic of asequential circuit, not a combinational one. A synthesized version of such a circuitwill have latches to implement the sequential nature of the description. That’s notcool, given that we’re trying to design a combinational circuit!Another way to view this requirement is for a combinational circuit to be synthesized, the loop in the description must be stateless — nothing can be rememberedfrom its previous execution.Following these two rules will help you in writing behavioral descriptions of combinational circuits that can be used equivalently for either simulation or synthesis.References: synthesis 2Tutorial: See the Tutorial Problems in Appendix A.3.1.3 Procedural Modeling of Clocked SequentialCircuitsProcedural models also can be used to describe finite state machines.
Figure 1.4 showsthe state transition diagram for a machine with three states, one input, and one output. The states are encoded by two ftip ftops namedandThe reset state isencoded with both ftip ftops being zero. Also shown in the figure is an implementation of the machine using D ftip ftops and gates.The traditional diagram of a finite state machine is shown in Figure 1.5. The diagramshows the state registers at the bottom. Their output is the current state of themachine. Their input is the next state of the machine which the registers will loadafter the clock edge. The next state is a combinational function of the current stateand the inputs.
The outputs are a combinational function of the current state and (insome systems) the inputs. This traditional structuring appears in the Verilog description. The next state and output combinational functions will be described behaviorallyin a single always block following the rules of the previous section. The state registerswill be described in a separate always block following a different set of rules.Verilog — A Tutorial Introduction151.3.1 Modeling Finite State MachinesA behavioral description of the machine in Figure 1.4 is shown in Example 1.6. Wehave named the output out, the input in, and have also provided ports for clock andreset.
Further, output out has also been declared to be a register. The current state ofthe machine has been named currentState. The definitionreg[1:0]currentState, nextState;indicates that currentState and nextState are two-bit vectors. The square brackets(“[ ]”) construct declares the range of bit numbers that each register has, the firstnumber being the most-significant bit and the second being the least-significant bit.out is also declared to be a register. It and nextState are assigned to in the combinational always block that implements the next state and output functions.
We haveintroduced the term vector in describing the registers nextState and currentState inthis example. Registers, such as out, and nets which are single-bit are said to be scalar.The Verilog Hardware Description Language16module fsm(output reg out,inputin, clock, reset);reg[1:0] currentState, nextState;always @(in, currentState) begin // the combinational portionout = ~currentState[1] & currentState[0];nextState = 0;if (currentState = = 0)if (in) nextState = 1;if (currentState = = 1)if (in) nextState = 3;if (currentState = = 3) beginif (in) nextState = 3;else nextState = 1;endendalways @(posedge clock, negedge reset) begin // the sequential portionif (~reset)currentState <= 0;elsecurrentState <= nextState;endendmoduleExample 1.6 A Synthesizable Finite State MachineThe first always block describes the combinational behavior of the output and nextstate logic.
The sensitivity list indicates that when a change occurs to in or currentState, then the begin…end statement is executed. The statements in the begin … endspecify the new values of the combinational outputs nextState and out. out is specified asout = ~currentState[1] & currentState[0];indicating that the complement (“~”) of bit 1 of currentState is AND-ed with bit 0 ofcurrentState.
The construct “currentState[1]” is called a bit-select of a vector — only asingle bit from the entire vector is used in this operation. nextState is calculated in thefollowing if statements. Consider the third one.Verilog — A Tutorial Introduction17if (currentState = = 3) beginif (in)nextState = 3;else nextState = 1;endThis states that if currentState is equal to 3 (i.e., 11 in two-bit binary, which corresponds to the bottom-left state in the state transition diagram of Figure 1.4), then thenew value of nextState depends on the value of in.
If in is TRUE, nextState is 3 (i.e.,11 in two-bit binary). Otherwise nextState is 01 in two-bit binary. The rest of thealways statement specifies how nextState is calculated when in other states.The first always block specifies a combinational circuit and it is useful to recheckthe combinational rules presented in section 1.2.2.
First, the only inputs to this combinational function are in and currentState. This can be checked by looking at theright-hand sides of the assignment statements and the conditional expressions in thealways block. No other named entities appear so these must be the inputs. To be combinational, the comma-separated event list must include in and currentState. It does.Secondly, the combinational outputs out and nextState must be declared as registersand assigned to in any execution of the always block. They are assigned to in the firsttwo statements of the always block, whether they are overwritten later or not.The second always block specifies the sequential portion of the finite statemachine. We have seen the procedural assignment “=” as it has been used in initialand always statements.
This always block introduces the non-blocking assignment “ <=”— an assignment that might best be described as a concurrent assignment — used ininitial and always statements with edge specifications (i.e., posedge or negedge). Fornow, just think of “ =” as an immediate assignment, and “ <=” as a delayed, concurrentassignment; shortly, we’ll explain the differences.The sensitivity list in the always block waits for one of two events to occur: either apositive edge on clock or a negative edge on reset. Think of a positive edge on a signalto be when it changes from a 0 to a 1, and a negative edge to be when a signal changesfrom a 1 to a 0. When one or both of these occur, the begin…end block is executed.Assume that a negative edge on reset occurs.
As the begin…end block begins executing, reset will be zero and thus currentState will be set to zero. As long as resetremains zero, even a positive edge on clock will only result in currentState being setto zero. This is the action of an asynchronous reset signal that overrides the clock on aftip ftop.Now consider the situation where reset is one and there is a positive edge on clock;the begin…end loop is executed but this time the else clause is taken. The assignmentThe Verilog Hardware Description Language18currentState <= nextState;loads currentState with the nextState. These statements model the positive edgetriggered behavior of a two-bit register made up of D-type ftip ftops.Now we can understand how the whole finite state machine model works.
Assumethat we are in state 0 (currentState is 0), reset is 1 (not asserted), clock is 0, and in is1. Given these values, then the two combinational outputs are: out is 0, and nextStateis 1. When the positive edge of the clock occurs, the second always block will executeand assign the value of nextState to currentState and then wait again for the nextpositive edge of clock or negative edge of reset. Since currentState just changed to 1,the first alway block will execute and calculate a new value for out and nextState. outwill become 1, and nextState will become 3 if in remains 1. If in becomes 0, the firstalways block will execute again, recalculating out and nextState independent of theclock edge; nextState will become 0, and out will become 0.References:@ 4.2; if 3.2; bit-select E.1, 3.2;1.3.2 Rules for Synthesizing Sequential SystemsIn addition to the rules listed in Section 1.2.2 for combinational circuits, there arerules for sequential systems.
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