Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 3
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The description may be simulated todetermine correctness, and some synthesis tools exist for automatic design. Indeed,the Verilog language provides the designer entry into the world of large, complex digital systems design. This first chapter provides a brief tour of the basic features of theVerilog language.1.1 Getting StartedThe Verilog language describes a digital system as a set of modules. Each of thesemodules has an interface to other modules as well as a description of its contents.
Amodule represents a logical unit that can be described either by specifying its internallogical structure — for instance describing the actual logic gates it is comprised of, orby describing its behavior in a program-like manner — in this case focusing on whatthe module does rather than on its logical implementation. These modules are theninterconnected with nets, allowing them to communicate.1.1.1 A Structural DescriptionWe start with a basic logic circuit from introductory logic design courses: part of abinary to seven segment display driver, shown in Example 1.1. A display driver takes amodule binaryToESeg;wireeSeg, p1, p2, p3, p4;regA,B,C,D;nand #1g1(p1, C,~D),g2 (p2, A, B),g3 (p3, ~B, ~D),g4 (p4, A, C),g5 (eSeg, p1, p2, p3, p4);endmoduleExample 1.1 A Binary To Seven Segment Display Driver (E Segment Only)four-bit binary input and drives the seven segments needed to display the digits zerothrough nine and the hexadecimal digits A through F.
Only the logic to drive segment E of a display is shown in the example.A Verilog description of this circuit is also shown in Example 1.1. The descriptionshows the basic definition of a module — in this case, of a module named binaryToESeg. Each module definition includes the keyword module followed by the moduleVerilog — A Tutorial Introduction3name and is terminated by the endmodule statement. The second line of this definitionspecifies the names of wires used to transmit logic values among the submodules ofthis module. The third line declares the names of storage elements that will hold values. These registers are an abstraction of a flip flop circuit element.The fifth line, and its continuation onto lines 6 through 10, instantiates five NANDgates, each having a delay of one time unit.
NAND gates are one of the predefined logicgate types in the language — the others, including AND, OR, and XOR, are detailedlater. This statement specifies that five gates, called g1 through g5, exist in the circuit.The “#1” indicates that they each have a delay of one time unit. Finally, the labels inthe parentheses indicate the wires and registers to which the gates are connected.
Thefirst label in the parentheses is the gate’s output and the others are inputs. The NOToperator (“~”) is used to specify that the complement of a value is connected to theinput. The wire, register, and instance names are included in the schematic drawing tofurther clarify the correspondence between the logic diagram and its equivalent Verilog description.Although this example is simple, it illustrates several important points about theVerilog language. The first is the notion of module definition versus module instantiation. Using the module statement, as shown in the above example, we define a moduleonce specifying all of its inner detail. This module may then be used (instantiated) inthe design many times.
Each of these instantiations are called instances of the module; they can be separately named and connected differently. Primitive gates, like theNAND, are predefined logic primitives provided by the language. They are presented inmore detail in Chapter 6.The gates are connected by nets. Nets are one of the two fundamental data types ofthe language (registers are the other), and are used to model an electrical connectionbetween structural entities such as gates.
A wire is one type of net; others includewired-AND, wired-OR, and trireg connections. The different net types are described inmore detail in Chapters 6 and 10.In this example, NAND gates were used to build the binaryToESeg module. ThisbinaryToESeg module, if it had input/output ports, could then be used in anothermodule by instantiating it there, and so on.
The use of hierarchical descriptions allowsus to control the complexity of a design by breaking the design into smaller and moremeaningful chunks (i.e. submodules). When instantiating the submodules, all weneed know about them is their interface; their potentially complex implementationdetails are described elsewhere and thus do not clutter the current module’s description.As a final comment, we should point out that the designation of A, B, C, and D asregisters might seem anomalous. One would think that these would be inputs tomodule binaryToESeg, and that the value eSeg would be an output.
These will beThe Verilog Hardware Description Language4changed to inputs and outputs in a later example. But for now, we will keep the register definitions as they will aid in simulation in the next section.References: gate primitives 6.2.1; net specification 6.2.31.1.2 Simulating the binaryToESeg DriverExample 1.2 shows a more complete module definition for binaryToESeg calledbinaryToESegSim. The example includes statements that will provide stimulus to theNAND gate instances, and statements that will monitor the changes in their outputs.Although all possible input combinations are not provided, the ones shown will illustrate how to provide input stimuli.module binaryToESegSim;wireeSeg, p1, p2, p3, p4;regA,B,C,D;nand #lg1 (p1,C,~D),g2 (p2, A, B),g3 (p3, ~B, ~D),g4 (p4, A, C),g5 (eSeg, p1, p2, p3, p4);initialbegin// two slashes introduce a single line comment("A = %b B = %b C = %b D = %b, eSeg = %b",A,B,C,D, eSeg);//waveform for simulating the binaryToESeg driver#10 A = 0; B = 0; C = 0; D = 0;#10 D = 1;#10 C = 1; D = 0;#10endendmoduleExample 1.2 binaryToESeg Driver To Be SimulatedA simulator for a digital system is a program that executes the statements inExample 1.2’s initial statement (and as we will see in later examples, the always statement), and propagates changed values from the outputs of gates and registers to othergate and module inputs.
A simulator is further characterized by its ability to keeptrack of time, causing the changed values to appear at some specified time in theVerilog — A Tutorial Introduction5future rather than immediately. These future changes are typically stored in a timeordered event list. When the simulator has no further statement execution or valuepropagation to perform at the current time, it finds the next time-ordered event fromthe event list, updates time to that of the event, and executes the event. This eventmay or may not generate events at future times.
This simulation loop continues untilthere are no more events to be simulated or the user halts the simulation by someother means.Example 1.2 differs fromExample 1.1 with the inclusionof the initial statement to drivethe simulation. The simulatorbegins the simulation by starting the execution of the initialstatement. The keywords beginand end bracket the individualstatements that are part of theinitial statement.
The results ofthe simulation of this example are shown in Figure 1.1.The first statement in the initial is a simulation command to monitor (and print) aset of values when any one of the values changes. In this case, the time is printedrequests that the current time be printed) and then the quoted string is printedwith the values of A, B, C, and D substituted for the %b (for binary) printing controlin the string. Betweenand the quoted string are several extra commas. One isneeded to separateand the quoted string; the extras each introduce an extraspace in the printout. When issued, the monitor command prints the current values inthe design, and will automatically print later when at least one of the values in its listchanges.
(However, it will not print when onlychanges.) As shown inFigure 1.1, they initially print as x. When the simulator starts, all values are unknownwhich is indicated by the x. The first value on the line is the time.The initial statement continues by scheduling four events to occur in the future.The statements:#10 A = 0; B = 0; C = 0; D = 0;specify that registers A, B, C, and D will each be loaded with zero 10 time units fromthe current time.
The way to think about the execution of this line is that the simulator suspends the execution of this initial statement for 10 time units. The simulatorsees no other action at the current (zero) time and goes to the next event in the timeordered event list, which happens to be this statement.
Thus the simulator reactivatesthe initial statement. At that time, time 10, the initial statement is reactivated fromwhere it suspended and the next statement is executed. Indeed, it continues executing6The Verilog Hardware Description Languageon the next line where the simulator sees the next #10. At this point the initial statement is suspended, waiting for ten more time units.But at the current time (time 10), the changed values for A, B, C, and D are propagated. By propagation, we mean that every primitive gate that is connected to any ofthese is notified of the change. These gates may then schedule their outputs to changein the future. Because the gates in this example are defined to have a time delay of 1,their output changes will be propagated one time unit into the future (at time 11); thesimulator schedules these values to be assigned and propagated then.As mentioned above, the initial statement continued executing until it found thedelay on the next line which specifies that in 10 more time units (i.e., at time 20), Dwill be loaded with a one.
The initial block is suspended and scheduled to wake up attime 20. The simulator looks for the next event in time, and it sees that four NANDgates (g1 through g4) are scheduled to change their output values at time 11 andpropagate them to the final NAND gate, g5.Interestingly, gates g1 through g4 should update their outputs at the same time.Indeed, they will all happen at the same “simulated time”, in this case time 11.
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