Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 10
Текст из файла (страница 10)
You must have one module containing another module.E. Simulate and verify your design of part D.34The Verilog Hardware Description LanguageF. Re-design and re-simulate the survivor_II detector from scratch, usingmuxes. For this, design and simulate a Verilog all-NAND implementation forwhich you must use an all-NAND 8x1 mux with gate, rat, naked on the selectlines (in that order). You must use one module for the mux, another module forthe external circuitry to the mux (all NAND), and a third containing module (thesurvivor_II module).
Say why your simulation results that show your designimplements the detector correctly.Design and simulate a mixed logic circuit to implement the word problem. TheSteelers are not having a very good season this year, to say the least. Some fanshave proposed the following logic to predict if the Steelers will their next game.The Steelers will win their next game (Win_L) if hell freezes over (Hell_L isasserted and Warm_H is de-asserted) or if the other team is locked in theirhotel rooms (Lock_L is asserted) and someone threw away the key (Key_L isde-asserted). The Steelers will also win if the other team lets them (Trying_L isde-asserted). The Steelers will also win if they are playing a high school team(High_H is asserted) where all of the good players are on academic probation(Smart_L is de-asserted).
Simulate your design using only primitive gates -structural Verilog. Clearly justify how your simulation verifies your design!1.16 Design and simulate a mixed logic circuit to implement the following wordproblem with logic to help decide whether or not to buy hotdogs at the localhotdog stand.It is worth buying hot dogs (Hot_L) on a weekday (Week_H) whenever it islunchtime (Lunch_L) or after midnight (Midnight_H), but only if none ofyour Professors are swimming in the pool (No_Profs_L) and the person behindthe counter does not have a tatoo that says “Mother” (No_Tatoo_H).
Simulateyour design using only primitive gates — structural Verilog. Clearly justify howyour simulation verifies your design!1.152Logic SynthesisIn this chapter, the use of the language as an input specification for synthesis is presented. The concern is developing a functionally correct specification while allowing asynthesis CAD tool to design the final gate level structure of the system.
Care must betaken in writing a description so that it can be used in both simulation and synthesis.2.1 Overview of SynthesisThe predominate synthesis technology in use today is logic synthesis. A system is specified at the register-transfer level of design; by using logic synthesis tools, a gate levelimplementation of the system can be obtained. The synthesis tools are capable ofoptimizing a design with respect to various constraints, including timing and/or area.They use a technology library file to specify the components to be used in the design.2.1.1 Register-Transfer Level SystemsA register-transfer level description may contain parts that are purely combinationalwhile others may specify sequential elements such as latches and flip flops. There mayalso be a finite state machine description, specifying a state transition graph.36The Verilog Hardware Description LanguageA logic synthesis tool compiles a register-transfer level design using two mainphases.
The first is a technology independent phase where the design is read in andmanipulated without regard to the final implementation technology. In this phase,major simplifications in the combinational logic may be made. The second phase istechnology mapping where the design is transformed to match the components in acomponent library. If there are only two-input gates in the library, the design is transformed so that each logic function is implementable by a component in the library.Indeed, synthesis tools can transform one gate level description into another, providing the capability of redesigning a circuit when a new technology library is used.The attraction of a logic synthesis CAD tool is that it aids in a very complex designprocess.
(After all, did your logic design professor ever tell you what to do when theKarnaugh map had more than five or six variables!) These tools target large combinational design and different technology libraries, providing implementation trade-offsin time and area. Further, they promise functional equivalence of the initial specification and its resulting implementation. Given the complexity of this level of design,these tools improve the productivity of designers in many common design situations.To obtain this increased productivity, we must specify our design in a way that itcan be simulated for functional correctness and then synthesized. This chapter discusses methods of describing register-transfer level systems for input to logic synthesis tools.2.1.2 DisclaimerThe first part of this chapter defines what a synthesizable description for logic synthesisis.
There are behaviors that we can describe but that common logic synthesis tools willnot be able to design. (Or they may design something you’d want your competitor toimplement!) Since synthesis technology is still young, and the task of mapping anarbitrary behavior on to a set of library components is complex, arbitrary behaviorspecifications are not allowed as inputs to logic synthesis tools.
Thus, only a subset ofthe language may be used for logic synthesis, and the style of writing a descriptionusing that subset is restricted. The first part of this chapter describes the subset andrestrictions commonly found in logic synthesis specification today. Our discussion oflogic synthesis is based on experience using current tools. If you use others, your mileage may vary. Read the synthesis tool manual closely.Logic Synthesis372.2 Combinational Logic Using Gates andContinuous AssignUsing gate primitives and continuous assignment statements to specify a logic function for logic synthesis is quite straightforward.
Examples 2.1 and 2.2 illustrate twosynthesizable descriptions in this style. Both of the examples implement the samecombinational function; the standard sum-of-products specification is:Essentially, logic synthesis tools read the logic functionality of the specification andtry to optimize the final gate level design with respect to design constraints and libraryelements. Even though Example 2.1 specifies a gate level design, a logic synthesis toolis free, and possibly constrained, to implement the functionality using different gateprimitives. The example shows a different, but functionally equivalent, gate leveldesign. Here, the technology library only contained two-input gates; the synthesistool transformed the design to the implementation on the right of the example.
Otherdesigns are possible with alternate libraries and performance constraints.module synGate(output f,input a, b, c);andA (a1, a, b, c);andB (a2, a, ~b, ~c);andC (a3, ~a, o1);orD (o1, b, c);orE (f, a1, a2, a3);endmoduleExample 2.1 A Description and Its Synthesized ImplementationThe example does not contain delay (#) information, illustrating one of the keydifferences between writing Verilog descriptions for simulation and synthesis. In simulation, we normally provide detailed timing information to the simulator to help thedesigner with the task of timing verification.
A logic synthesis tool will ignore thesetiming specifications, using only the functional specification provided in the description. Because timing specifications are ignored, having them in a description couldgive rise to differences in simulating a design being input to a logic synthesis tool versus simulating the resulting implementation.Consider gate instance A in Example 2.1. If it had been specified as:The Verilog Hardware Description Language38and#5A (a1, a, b, c);then simulation of the description would have shown a 5 time unit delay betweenchanges on the input to changes on the output of this gate.
The implementationshown in Example 2.1 does not have a gate corresponding to A. Thus, the timing ofthe simulation of that implementation would be different. Logic synthesis does nottry to meet such timing specifications. Rather, synthesis tools provide means of specifying timing requirements such as the clock period.
The tool will then try to designthe logic so that all set-up times are met within that clock period.module synAssign(output f,input a, b, c);assignendmodulef = (a & b & c) | (a &~b &~c) | (~a & (b | c));Example 2.2 A Synthesizable Description Using Continuous AssignUsing a continuous assign statement, as shown in Example 2.2, is similar to specifying logic in Boolean algebra, except Verilog has far more operators to use in thespecification. The assign statement allows us to describe a combinational logic function without regard to its actual structural implementation — that is, there are noinstantiated gates with wires and port connections.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
