Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 5

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However, in Verilog, each module has its own name space; each A in this example is known onlyVerilog — A Tutorial Introduction11within the module in which it is declared. Thus the two A’s are names of distinct entities. In this example though, wire w2 connects them making them electrically thesame. Thus a change made to register A will propagate across wire w2 to the A inputsof g2 and g4.References: synthesis 2.

namespaces 3.6Tutorial: See the Tutorial Problems in Appendix A.2.1.2 Behavioral Modeling of CombinationalCircuitsOur view so far of the Verilog language has mainly highlighted its capabilities ofdescribing structure — module definitions, module instances, and their interconnections. We have only had a very cursory view of the language’s capability for describinga module’s function behaviorally.A behavioral model of a module is an abstraction of how the module works.

Theoutputs of the module are described in relation to its inputs, but no effort is made todescribe how the module is implemented in terms of structural logic gates.Behavioral models are useful early in the design process. At that point, a designer ismore concerned with simulating the system’s intended behavior to understand itsgross performance characteristics with little regard to its final implementation. Later,structural models with accurate detail of the final implementation are substituted andresimulated to demonstrate functional and timing correctness. In terms of the designprocess, the key point is that it is often useful to describe and simulate a module usinga behavioral description before deciding on the module’s actual structural implementation. In this way, the designer can focus on developing the right design (i.e.

one thatworks correctly with the rest of a system and has the intended behavior) before continuing. This behavioral model can then be the starting point for synthesizing severalalternate structural implementations of the behavior.Behavioral models are described in a manner similar to a programming language.As we will see, there are many levels of abstraction at which we may model the behavior of a system.

For large systems, we may describe the algorithm that is to be implemented. Indeed, the algorithm may be an almost direct translation from aprogramming language such as C. At a lower level of abstraction, we may describe theregister-transfer level behavior of a circuit, specifying the clock edges and preconditions for each of the system’s register transfers. At a still lower level, we may describethe behavior of a logic gate or ftip ftop. In each case, we use the behavioral modelingconstructs of the Verilog language to specify the function of a module without directlyspecifying its implementation.The Verilog Hardware Description Language121.2.1 Procedural ModelsExample 1.5 introduces the behavioral approach to modeling combinational logic.The functionality of the module is described in terms of procedural statements ratherthan with gate instantiations.

The always statement, introduced here, is the basis formodeling behavior. The always statement, essentially a “while (TRUE)” statement,includes one or more procedural statements that are repeatedly executed. These procedural statements execute much like you would expect a software program to execute:changing register values using the “=” assignment, and executing loops and conditional expressions. Note that within the always statement, all assignments using “=”are made to entities declared as registers.

This was also true of the initial statementsseen earlier.module binaryToESeg_Behavioral(output reg eSeg,inputA, B, C, D);always @(A, B, C, D) begineSeg = 1;if (~A & D)eSeg = 0;if (~A & B & ~C)eSeg = 0;if (~B & ~C & D)eSeg = 0;endendmoduleExample 1.5 A Behavioral Model of binaryToESegThe example shows a behavioral model of our binary to seven segment displaydriver.

The port declarations are the same as before. We have also declared one register, eSeg. This is the register we will make assignments to within the always statement, and it will also be the output of the purely combinational circuit. This alwaysstatement starts off with an event control “@” statement. The statement:@(A, B, C, D) begin … endstates that the simulator should suspend execution of this always block until a changeoccurs on one of the named entities.

Thus, the value of each of A, B, C, and D is sampled when this statement executes. The simulator then waits for a change to occur onany of these named inputs. When a change occurs on any one (or more) of these, thenexecution will continue with the next statement — in this case what is contained inthe begin … end block.Verilog — A Tutorial Introduction13When a change occurs and execution continues, the assignment and if statementsshown execute much like you would expect in a programming language. In this case,the statements describe how the output (eSeg) is to be calculated from the inputs.Comparing the statements to the Karnaugh map, one can see that the output is set toone.

Then, if one of the zeros of the function is on the input, eSeg is set back to zero.When the begin … end block finishes, the always block restarts again, sampling thelisted values (A, B, C, or D) and then waiting for a change on one or more of them.At this point, the simulator will propagate the final value of eSeg to other parts of thedesign connected to it.There are two features of the example to note. First, it describes the same functional behavior as the previous example, but there is no mention of the actual gatelevel implementation; the model is behavioral.Secondly, the fact that eSeg is declared as a register might make you think that it isnot a combinational circuit.

But, consider the action of this module when only looking at its ports from the outside. You will quickly conclude that if there is any changeon any of the inputs, the output will be re-evaluated based only on the module inputs.The previous value of eSeg does not matter. This is a fundamental characteristic of acombinational circuit. From the outside of the module, it’s clear that this has thebehavior of a combinational circuit.References: always 3.1, if 3.21.2.2 Rules for Synthesizing Combinational CircuitsSynthesis tools read a behavioral description of a circuit and automatically design agate level structural version of the circuit. Thus, given Example 1.5 as an input specification, a synthesis tool might produce the design specified in Example 1.3; otherimplementations are possible too.Not just any sequence of behavioral statements is appropriate for synthesis of combinational circuits.

To use synthesis tools, you need to be very careful with how thedescription is written. The rules for synthesizing combinational circuits are brieflysummarized here but they are covered in far more detail in Chapter 2. To be sure thatyour synthesized circuit will be combinational:Check that all inputs to your combinational function are listed in the controlevent’s sensitivity list (the comma-separated list of names).

That way, if one ofthem changes, the output is re-evaluated. Section 2.3 discusses the use of the @(*)constructto automatically specify all of the inputs.The need for this requirement stems from the definition of a purely combinationalcircuit. The output of a combinational circuit is a function of the current inputs; ifone changes, the output should be re-evaluated.The Verilog Hardware Description Language14Check that there is no way to execute the begin…end loop without assigning avalue to the combinational output (eSeg in this example).

That is, the output mustbe assigned a value at least once in every execution of the begin...end loop. InExample 1.5, line 6 (eSeg = 1;) assigns a value to eSeg and satisfies this requirement.To understand the need for this requirement, consider the situation where youexecute the begin…end loop and don’t assign to the output. In this case, the circuitneeds to remember the previous value. Thus, the output is a function of the current inputs and the previous output.

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