Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 2
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The first part ofthe book contains a tutorial introduction to the language which is followed by a chapter on its use for logic synthesis. The second part of the book, Chapters 3 through 6,provide a more rigorous presentation of the language’s behavioral, hierarchical, andlogic level modeling constructs. The third part of the book, Chapters 7 through 11,covers the more specialized topics of cycle-accurate modeling, timing and eventdriven simulation, user-defined primitives, and switch level modeling. Chapter 11suggests two major Verilog projects for use in a university course. One appendix provides tutorial discussion for beginning students.
The others are reserved for the dryertopics typically found in a language manual; read those at your own risk.Have fun designing great systems…always,Donald E. ThomasPhilip R. MoorbyMarch 2002From the Old to theNewThis book as been updated so that the new features of IEEE Std. 1364-2001 arealways used even though the “old ways” of writing Verilog (i.e. IEEE Std.
1364-1995)are still valid. In this preface, we show a few side-be-side examples of the old and new.Thus, this section can stand as a short primer on many of the new changes, or as a reference for how to read “old code.” Throughout this preface, cross references are madeto further discussion in the earlier parts of the book. However, not all changes areillustrated in this preface.Ports, Sensitivity Lists, and ParametersPort declarations can now be made in “ANSI C” style as shown in Example P.1. Inthe old style, the port list following the module name could only contain the identifiers; the actual declarations were done in separate statements.
Additionally, only onedeclaration could be made in one statement. Now, the declarations can be made in theopening port list and multiple declarations can be made at the same time. Multipledeclarations are illustrated in the declaration of eSeg being an “output reg” in the newstandard; previously this took two statements as shown on the right of the example(See Section 5.1). This style of declaration also applies to user defined primitives (Seechapter 9). These two module descriptions are equivalent.The Verilog Hardware Description Languagexviiimodule binaryToESeg_Behavioral(output reg eSeg,inputA, B, C, D);always @ (A, B, C, D) begineSeg = 1;if(~A & D)eSeg = 0;if(~A & B & ~C)eSeg = 0;if(~B & ~C & D)eSeg = 0;endendmoduleExample P.1 2001 Standard (Left);Previous 1995 (Right)Example P.1 also shows a simpler wayto describe sensitivity lists.
Previously, thelist was an or-separated list of identifiersas shown on the right of the figure. Now,the list can be comma-separated (SeeSection 4.2.1). Additionally, if the intentis to describe a combinational circuit usingan always block, the explicit sensitivity listcan replaced with a @(*) as illustrated inExample P.2. The module descriptions inExamples P.1 and P.2 describe equivalentfunctionality. (See Section 2.3.1.)module binaryToESeg_Behavioral(eSeg, A, B, C, D);output eSeg;input A, B, C, d;regeSeg;always @ (A or B or C or D)begineSeg = 1;if (~A & D)eSeg = 0;if (~A & B & ~C)eSeg = 0;if (~B & ~C & D)eSeg = 0;endendmodulemodule binaryToESeg_Behavioral(output reg eSeg,inputA, B, C, D);always @(*) begineSeg = 1;if(~A & D)eSeg = 0;if(~A & B & ~C)eSeg = 0;if(~B & ~C & D)eSeg = 0;endendmoduleIf the module is parameterized, thenthe list of parameters is introduced anddeclared before the port list so that someExample P.2 Sensitivity List Using@(*)of the port specifications can be parameterized.
(See Section 5.2.) This is illustrated in Example P.3. The new standard also allows for parameters to be over-riddenby name. The old style of instantiating module xorx of Example P.3 would bexorx #(7, 12) x1(a,b,c);where the new value of width is 7 and delay is 12. With the new style, individualparameters can be overridden —xixmodule xorx#(parameter width = 4,delay = 10)(output [1:width] xout,input [1:width] xin1,xin2);module xorx (xout, xin1, xin2);parameter width = 4,delay = 10;output [1:width] xout;input [1:width] xin1,xin2;assign #(delay)xout = xin1 ^ xin2;endmoduleassign #(delay)xout = xin1 ^ xin2;endmoduleExample P.3 Parameter Definition with 2001 Standard (Left) and 1995 (Right)xorx #(.delay(8)) x2 (a,b,c);where delay is changed to 8 and width remains at 4.Functions and tasks may also be declared using the combined port and declarationstyle.
Using the 1995 style, a function with ports would be defined asfunction [11:0] multiply;input [5:0] a, b;endfunctionThe new 2001 style allows the definition within the port list; declarations may be ofany type (See Section 3.5).function [11:0] multiply(input [5:0] a, b);endfunctionOther ChangesMany of the other changes are illustrated throughout the book. They are referencedhere.Functions may now be declared recursive, constant, and signed (Section 3.5).Tasks may now be declared automatic (Section 3.5).Initial values may now be specified in declarations (See Section 1.4.1).Implicit net declarations are now applied to continuous assignments (Section 6.3).Also, they may now be disabled (Section 6.2.3) with keyword none.Variable part-selects (Section 3.2).xxThe Verilog Hardware Description LanguageArrays may now be multidimensional and of type net and real.
Bit and part-selectsare allowed on array accesses (Section E.2).Signed declarations. Registers (Section E.1), nets (Section 6.2.3), ports(Section 5.1), functions (Sections 3.5.2), parameters (Section 5.2) and sized numbers (Section B.3) may be signed. signed and unsigned system functions have beenadded (Section C.1).Operators. Arithmetic shift operators and a power operator have been added(Section C.1).Parameters. Local parameters may now be defined. Parameters may now be sizedand typed.
(Section 5.2)Attributes have now been added to specify additional information to other tools(Section 2.3.4). Details of using attributes is left to the user manuals of the toolsthat define them. Attribute specification is left out of the BNF illustrations in therunning text. However they are included in appendix G.Generate blocks have now been added to aid in iterative specification.(Section 5.4)AcknowledgmentsThe authors would like to acknowledge Accellera (http://www.accellera.org), whoserole it is to maintain and promote the Verilog standard, and the many CAD tooldevelopers and system designers who have contributed to the continuing developmentof the Verilog language.
In particular, the authors would like to thank Leigh Brady forher help in reviewing earlier manuscripts.The authors would also like to thank JoAnn Paul for her help and suggestions onthe introduction and the the chapter questions, John Langworthy for helping us focusthe tutorial material in appendix A toward students in a sophomore course, TomMartin for his help in developing the exercises in chapter 11, and H.
Fatih Ugurdagfor providing us with Example 7.5. We also acknowledge many practicing engineers,faculty and students who have used the book and provided feedback to us on it.Finally, we wish to acknowledge Margaret Hanley for the cover and page formatdesigns.The Institute of Electrical and Electronics Engineers maintains the Verilog Hardware Description Language standard (IEEE #1364-2001).
We wish to acknowledgetheir permission for including the formal syntax specification in appendix G. Complete copies of the standard may be obtained through http://standards.ieee.org.1Verilog —A Tutorial IntroductionDigital systems are highly complex. At their most detailed level, they may consist ofmillions of elements, as would be the case if we viewed a system as a collection oflogic gates or pass transistors. From a more abstract viewpoint, these elements may begrouped into a handful of functional components such as cache memories, floatingpoint units, signal processors, or real-time controllers.
Hardware description languages have evolved to aid in the design of systems with this large number of elements and wide range of electronic and logical abstractions.The creative process of digital system design begins with a conceptual idea of a logical system to be built, a set of constraints that the final implementation must meet,and a set of primitive components from which to build the system. Design is an iterative process of either manually proposing or automatically synthesizing alternativesolutions and then testing them with respect to the given constraints.
The design istypically divided into many smaller subparts (following the well-known divide-andconquer engineering approach) and each subpart is further divided, until the wholedesign is specified in terms of known primitive components.The Verilog language provides the digital system designer with a means of describing a digital system at a wide range of levels of abstraction, and, at the same time, provides access to computer-aided design tools to aid in the design process at these levels.The language supports the early conceptual stages of design with its behavioral constructs, and the later implementation stages with its structural constructs. During thedesign process, behavioral and structural constructs may be mixed as the logical struc-The Verilog Hardware Description Language2ture of portions of the design are designed.
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