Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 8
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The counter output in Example 1.10 isconnected to the binaryToESeg module. However, this module is defined to have five1-bit ports.module binaryToESeg (eSeg, A, B, C, D);In the board module, we define a 4-bit wire count that connects to m16. When weconnect it to binaryToESeg we need to connect each bit (A through D) individually.This we do with a bit-select of the count wire, specifying the appropriate bit for eachconnection. A bit-select allows us to specify a single bit in a register or wire that hasbeen declared to be a vector. Thus, the connection in to binaryToESeg in moduleboard becomesThe Verilog Hardware Description Language24binaryToESegdisp(eSeg, count[3], count[2], count[l], count[0]);This connects count[3] to A, count[2] to B,count[1] to C, and count[0] to D as illustrated in Figure 1.8.
Think of it as having acable that contains four bundled wires; thebundling is then broken to expose the separate wires.Alternately, as shown in Example 1.11,we could have declared four scalar (singlebit) wires and then concatenated them together when connecting to the m16 module.Here we define scalar wires w3, w2, w1, w0 and we connect them to ports A, B, C,and D of binaryToESeg. However, module m16 expects a 4-bit vector to connect toits ctr port. The concatenation operator “{w3, w2, w1, w0}” combines w3, w2, w1,and w0; They are grouped (concatenated) together and treated as one 4-bit bundlewhen connecting to m16.module boardWithConcatenation;wireclock, eSeg, w3, w2, w1,w0;m16counter({w3, w2, w1, w0}, clock);m555clockGen (clock);binaryToESeg disp(eSeg, w3, w2, w1, w0);initial("count=%d, eSeg=%d", {w3, w2, w1, w0}, eSeg);endmoduleElxample 1.11 An Alternate Top-Level ModuleIf the module definitions in Examples 1.3, 1.8, 1.9, and 1.10 are compiledtogether, they form a complete description that can be simulated.
The simulationtrace from simulating these combined examples for 802 time units is shown inFigure 1.9.Initially, all values in the system at time 0 are unknown. Then, the initial andalways blocks, as well as the initializations in the declarations (e.g., the initializationof ctr), are enabled to run; they begin running in an arbitrary order. The initial statements in m555 begin by delaying for #5 and #50 respectively. The always in m16begins by waiting for a positive edge on the clock. The initilization in the declarationsets ctr to 1.
The gate primitives in binaryToESeg wait for a change on their inputs.The initial statement in board also runs. We can see that the initialization in m16Verilog — A Tutorial Introduction25runs first, setting ctr to 1. Then the initial in board runs, executing thestatement and printing the first line in the figure. (If thehad executedbefore the initialization of ctr, count would have printed as x.)Given that ctr (count) is set to 1 attime 0, two time units later eSeg changesits value to 0 (eSeg is off when the ctr 1is being displayed). At time 5, clockchanges from x to 1. In Verilog, this isinterpreted as a positive edge, whichchanges ctr (count) to 2.
Two time unitslater, at time 7, eSeg changes to 1because the eSeg is on when displayingthe ctr 2. At time 50, clock changes to 0.However, this is not shown in our simulation because we were not monitoringthe change in the clock. At time 100,clock changes to 1, creating a positiveedge on clock and incrementing ctr(count), ctr changes to 3 and eSegchanges appropriately two time unitslater. The simulation continues asshown.Although the initial statement is necessary for simulating Example 1.8, it isnot necessary to synthesize it. In fact, logic synthesis ignores initial blocks and initializations in declarations.References: module instantiation 5.1; net declaration 6.2.3; always 3.1;F.11.4.4 Tying Behavioral and Structural Models TogetherIn several examples, we connected together modules that were defined differently.Some of them were defined structurally using only gate level primitives.
And somewere defined behaviorally, using always blocks. This is a powerful aspect of the language because it allows us to model parts of a system at a detailed level (i.e., the structural models) and other parts at a less detailed level (the behavioral models). At thestart of a design project, most of the system will be at the behavioral level. Then partswill be detailed into structural models. The final simulation could then be with allmodules defined at the gate level for accurate timing and functional simulation. Thusthe language aids in the complete design process, allowing a design to evolve frombehavioral through to structural in evolutionary steps.26The Verilog Hardware Description LanguageExample 1.10 and its submodules partially illustrate how behavioral and structuralelements connect together. In this example, the structural binaryToESeg module inExample 1.3 is connected together with the behavioral m16 module fromExample 1.8.
The register ctr in m16 is declared to be an output. Any changes to ctrare propagated through the module ports and eventually to gate inputs. Thus we seethat registers specified in behavioral models can drive the inputs of gate primitives.This need not be done in separate modules.Indeed we could combine thefunctionality of these two modules as shown in Example 1.12.Here within one module we haveboth structural and behavioralcomponents.
Anytime ctr isupdated, the gates g1 through g4will re-evaluate their outputbecause their inputs are connected to ctr. Thus, the “output”of an always block — the valuesin the registers assigned to by thealways block — can be used asinputs to gate level primitives.module counterToESeg(output reg eSeg,inputclock);reg[3:0]ctr = 0;always @(posedge clock)ctr <= ctr + 1;nand #1g1 (pl, ctr[l], ~ctr[0]),g2 (p2, ctr[3], ctr[2]),g3 (p3, ~ctr[2], ~ctr[0]),g4 (p4, ctr[3], ctr[l]),g5 (eSeg, p1, p2, p3, p4);endmoduleExample 1.12 Behavior Driving StructureIn like manner, the outputs ofgate level primitives can be used as“inputs” to always blocks as illustrated in Example 1.13.
Here wealter the original structural binarytoESeg module to producemixedUpESegDriver. The changeis that the final NAND gate thatNAND-ed together the outputs ofthe other NAND gates has beendescribed behaviorally using analways block. This always blockwaits for any change on p1, p2, p3,or p4. When a change occurs, thebehavioral statement calculatestheir NAND storing it in registereSeg. This value is the combinational output of the module. Thusmodule mixedUpESegDriver(output reg eSeg,inputA, B, C, D);nand #1g1 (p1, C, D),g2 (p2, A, ~B),g3 (p3, ~B, ~D),g4 (p4, A, C);always @(p1, p2, p3, p4)eSeg = ~(p1 & p2 & p3 & p4);endmoduleExample 1.13 Structure Driving BehaviorVerilog — A Tutorial Introduction27the outputs of gate primitives can drive the inputs — values on the right-hand side ofbehavioral expressions — of behavioral blocks.These examples serve to illustrate the two main data types in the language, registers and nets, and how they work together.
Gate primitives drive their outputs ontonets (in our examples, wires). Gate inputs can either be other nets, or registers.Behavioral models, i.e., always blocks, change register values as a result of their execution. Their inputs can either be other registers, or nets driven by gate primitives.References: procedural assignment 3.1; continuous assignment 6.3; timing models 8.1Tutorial: See the Tutorial Problems in Appendix A.5.1.5 SummaryThis brief tour has illustrated the basic capabilities of the language. Important amongthese are:The ability to partition a design into modules which can then be further divideduntil the design is specified in terms of basic logic primitives.
This hierarchicalmodularization allows a designer to control the complexity of the design throughthe well-known divide-and-conquer approach to large engineering design.The ability to describe a design either in terms of the abstract behavior of thedesign or in terms of its actual logical structure. The behavioral description allowsfor early design activities to concentrate on functionality. When the behavior isagreed upon, then it becomes the specification for designing possibly several alternate structural implementations, possibly through the use of synthesis tools.The ability to synchronize concurrent systems.
The concurrent parts of a systemthat share data must synchronize with each other so that the correct information ispassed between the current parts. We illustrated how systems can be synchronizedto signal edges (e.g. a clock).This tutorial chapter was meant to give a quick introduction to the language. Assuch, many details were skimmed over with the goal of giving the reader a feel for thelanguage.
The approach was to present and describe examples that illustrate the mainfeatures and uses of the language.The goal of the later chapters is to cover the language and its uses in more depth,while still presenting the language with an example-oriented approach.
Our goal isnot to present the Verilog language just as a formal syntax specification. But, realizingthat the examples we give cannot illustrate the entire language syntax, we will beginintroducing some of the language’s formal syntax specification. This specification willprobably not be useful for the first-time reader. However, it will be invaluable for theThe Verilog Hardware Description Language28reference reader and description writer.
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