Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 13
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The while and forever loops are used for synthesizingsequential systems. The repeat loop is not allowed in any synthesizable specifications.Logic Synthesis47For loops allow for a repetitivemodule synXor8specificationasshownin(output reg [1:8] xout,Example 2.14 (Generate loops are[1:8] xin1, xin2);inputdiscussed in more detail inSection 5.4.) In this example, eachreg[1:8] i;iteration of the loop specifies a different logic element indexed by thealways @(*)loop variable i. Thus, eight xor gatesfor (i = 1; i <= 8; i = i + 1)are connected between the inputsxout[i] = xin1[i] ^ xin2[i];and the outputs. Since this is a speciendmodulefication of combinational logic, idoes not appear as a register in the Example 2.14 Using for to Specify an Arrayfinal implementation.The example illustrates several points about using for statements for specifyinglogic.
The for loop is highly structured, clearly specifying the step variable and its limits. It will have an index i that must either start with a low limit and step up to a highlimit, or start with a high limit and step down to a low limit. The comparison for endof loop may be <, >, <=, or >=, and the step size need not be one.
The general formshown below illustrates the count down version:for (i = highLimit; i >= lowLimit; i = i - step);Example 2.15 shows a more complex design. The design is of a digital correlatorwhich takes two inputs (message and pattern) and counts the number of bits thatmatch. If message was 8'b00001111 and pattern was 8'b01010101, then the numberof bits that match is four. At first glance this module appears to be a sequential algorithm.
However, the for loop specifies a cascade of adders summing up the correlations of each bit-pair; a combinational circuit results.The bitwidth of the inputs and outputs are parameterized. Starting with bit position zero, the two inputs are XNOR’d together producing their correlation — 1 if theinput bits are the same, else 0. The next iteration of the for loop specifies another correlation, this time of bit one of message and pattern; this correlation is added with theprevious result. The result of all iterations of the for loop is to specify dataWidth levels of adders.
A logic synthesizer can work hard on optimizing that! When simulated,the initialization to matchCount starts it at zero.References: Unallowed constructs 2.8, parameters 5.2, generate 5.4.The Verilog Hardware Description Language48module DigitalCorrelator#(parameterdataWidth = 40,countWidth = 6,)(output reg [countWidth-1:0] matchCount = 0,input[dataWidth-1:0] message, pattern);inti;always @(*) beginfor (i = 0; i < dataWidth; i = i + 1)matchCount = matchCount + ~(message[i] ^ pattern[i]);endendmoduleExample 2.15 Digital Correlator2.4 Inferring Sequential ElementsSequential elements are the latches and flip flops that make up the storage elements ofa register-transfer level system. Although they are a fundamental component of a digital system, they are difficult to describe to a synthesis tool; the main reason being thattheir behavior can be quite intricate.
The form of the description of some of these elements (especially flip flops) are almost prescribed so that the synthesis tool will knowwhich library element to map the behavior to.2.4.1 Latch InferencesLatches are level sensitive storage devices. Typically, their behavior is controlled by asystem wide clock that is connected to a gate input (G). While the gate is asserted(either high or low), the output of the latch follows the input D — it is a combinational function of D.
When the gate is unasserted, the output remembers the lastvalue of the D input. Sometimes these devices have asynchronous set and/or resetinputs. As we have seen in section 2.3.2, latches are not explicitly specified. Rather,they arise by inference from the way in which a description is written. We say thatlatches are inferred.
One example of an inferred latch was shown in Example 2.7.Latches are inferred using the always statement as a basis. Within an always statement, we define a control path to be a sequence of operations performed when executing an always loop. There may be many different control paths in an always block dueto the fact that conditional statements (e.g. case and if) may be used.
To produce acombinational circuit using procedural statements, the output of the combinationalLogic Synthesis49function must be assigned in each and every one of the different control paths. Thus,for every conceivable input change, the combinational output will be calculated anew.To infer a latch, two situations must existmodule synLatchResetin the always statement: at least one control(output regpath must exist that does not assign to an outinputg, d, reset);put, and the sensitivity list must not containany edge-sensitive specifications. The firstalways @(*)gives rise to the fact that the previous outputif (~reset)value needs to be remembered.
The secondleads to the use of level-sensitive latches (aselse if (g)opposed to edge-sensitive flip flops). Therequirement for memory is indicative of aendmodulesequential element where the previous state isremembered in a latch when the inputs spec- Example 2.16 Latch With Resetify this control path. A logic synthesis toolwill recognize this situation and infer that a latch is needed in the circuit. Assumingthat we are trying to describe a sequential element, leaving the output variable unassigned in at least one path will cause a latch to be inferred.Example 2.16 shows a latch withmodule synALUwithLatchedOutputa reset input. Although we have#(parameterWidth = 4)specified output to be a register,(output reg [Width-l:0]that alone does not cause a latch toinput[Width-l:0] a, b,be inferred. To see how the latchinputg, addsub);inference arises, note that in thecontrol flow of the always statealways @(*) beginment, not all of the possible inputif (g) begincombinations of g and reset areif (addsub)specified.
The specification says thatif there is a change on either g, d orelsereset, the always loop is executed. Ifendreset is zero, thenis set to zero. Ifendthat is not the case, then if g is one,endmodulethenis set to the d input. However, because there is no specifica- Example 2.17 ALU With Latched Outputtion for what happens when reset isone and g is zero, a latch is neededto remember the previous value ofThis is, in fact, the behavior of a level sensitivelatch with reset.
The latch behavior could also have been inferred using case or otherstatements.The latch synthesized does not need to be a simple gated latch; other functionalitycan be included as shown in Example 2.17. Here an ALU capable of adding and subtracting is synthesized with an output latch. The module’s width is parameterized.50The Verilog Hardware Description LanguageWhile gate g is TRUE, the outputwill follow the inputs, producing either the sumor difference on the output. Input addsub selects between the two functions.
When gis not TRUE, the latch holds the last result.2.4.2 Flip Flop InferencesFlip flops are edge-triggered storage devices.Typically, their behavior is controlled by apositive or negative edge that occurs on a special input, called the clock. When theedge event occurs, the input d is remembered and gated to the output They oftenhave set and/or reset inputs that may change the flip flop state either synchronously orasynchronously with respect to the clock. At no time is the output a combinationalfunction of the input d. These flip flops are not explicitly specified. Rather, they areinferred from the behavior.
Since some of their behavior can be rather complex, thereis essentially a template for how to specify it. Indeed some synthesis tools provide special compiler directives for specifying the flip flop type.Example 2.18 shows a synthesizable modelmodule synDFFof a flip flop. The main characteristic of a flip(output reg q,flop description is that the event expression oninputclock, d);the always statement specifies an edge. It is thisedge event that infers a flip flop in the finalalways @(negedge clock)design (as opposed to a level sensitive latch).q <= d;As we will see, an always block with an edgeendmoduletriggered event expression will cause flip flopsto be inferred for all of the registers assigned to Example 2.18 A Synthesizable DFlip Flopin procedural assignments in the always block.(Thus, an always block with an edge-triggeredevent expression cannot be used to define a fully combinational function.)Typically flip flops include reset signals to initialize their state at system start-up.The means for specifying these signals is very stylized so that the synthesis tool candetermine the behavior of the device to synthesize.
Example 2.19 shows a D flip flopwith asynchronous set and reset capabilities. In this example, the reset signal isasserted low, the set signal is asserted high, and the clock event occurs on the positiveedge of clock.Examples 2.18 and 2.19 both use non-blocking assignments in their specification.This specification allows for correct simulation if multiple instances of these modulesare connected together.Although the Example 2.19 appears straight-forward, the format is quite strict andsemantic meaning is inferred from the order of the statements and the expressionswithin the statements. The form of the description must follow these rules:Logic Synthesis51module synDFFwithSetReset(output reg q,inputd, reset, set, clock);always @(posedge clock, negedge reset, posedge set) beginif (~reset)q <= 0;else if (set)q <= 1;else q <= d;endendmoduleExample 2.19 A Synthesizable D Flip Flop With Set and ResetThe always statement must specify the edges for each signal.
Even though asynchronous reset and set signals are not edge triggered they must be specified thisway. (They are not edge triggered because q will be held at zero as long as reset iszero — not just when the negative edge occurs.)The first statement following the always must be an if.The tests for the set and reset conditions are done first in the always statementusing else-if constructs. The expressions for set and reset cannot be indexed; theymust be one-bit variables. The tests for their value must be simple and must bedone in the order specified in the event expression.If a negative edge was specified as in reset above, then the test should be:if (~reset) …orif (reset == 1'b0) …If a positive edge was specified as in set above, then the test should be:if (set) …orif (set == l'b1) …After all of the set and resets are specified, the final statement specifies the actionthat occurs on the clock edge.
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