Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 15
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We’ll use a method ofspecification known as finite state machine and datapath, or FSM-D. Our system willbe made up of two parts: a datapath that can do computations and store results in registers, and a finite state machine that will control the datapath.2.7.1 A Simple ComputationWe begin with a simple computation and show how to specify the logic hardwareusing Verilog. The computation is shown below in a C-like syntax:…for (x = 0, i = 0; i <= 10; i = i + 1)x = x + y;if (x < 0)y = 0;else x = 0;…The computation starts off by clearing x and i to 0.
Then, while i is less than or equalto 10, x is assigned the sum of x and y, and i is incremented. When the loop is exited,if x is less than zero, y is assigned the value 0. Otherwise, x is assigned the value 0.Although simple, this example will illustrate building larger systems.We’ll assume that these are to be 8-bit computations and thus all registers in thesystem will be 8-bit.2.7.2 A Datapath For Our SystemThere are many ways to implement this computation in hardware and we will focuson only one of them. A datapath for this system must have registers for x, i, and y.
Itneeds to be able to increment i, add x and y, and clear i, x, and y. It also needs to beable to compare i with 10 and x with 0. Figure 2.4 illustrates a datapath that couldexecute these register transfers.The name in each box in the figure suggests its functionality. Names with overbarsare control signals that are asserted low. Looking at the block labeled register i, we seethat its output (coming from the bottom) is connected back to the input of an adderwhose other input is connected to 1. The output of that adder (coming from the bottom) is connected to the input of register i. Given that the register stores a value andthe adder is a combinational circuit, the input to register i will always be one greaterthan the current value of register i.
The register also has two control inputs: iLoadand iClear. When one of these inputs is asserted, the specified function will occur atLogic Synthesis59the next clock edge. If we assert iLoad, then after the next clock edge register i willload and store its input, incrementing i. Alternately, iClear will load a zero into register i. The compare modules are also combinational and produce the Boolean resultindicated.The register transfers shown in our computation are x = 0, i = 0, y = 0, i = i + 1, andx = x + y. From the above description of how the datapath works, we can see that all ofthe register transfers in our computation can be executed on this datapath.
Further, allof the conditional values needed for branching in the FSM are generated in the datapath.The FSM shown on the left sequences through a series of states to cause the computation to occur. The FSM’s outputs are yLoad, yClear, xLoad, xClear, iLoad, andiClear. Its inputs are x<0 and i<=10. A master clock drives the state registers in theFSM as well as the datapath registers. A reset signal is also connected.60The Verilog Hardware Description Language2.7.3 Details of the Functional Datapath ModulesThe datapath is made upmodule registerof three basic modules:#(parameterWidth = 8)registers, adders, and(output reg [Width-1:0] out,comparators.
The registerinput[Width-1:0] in,module definition isinputclear, load, clock);shown in Example 2.24.Looking first at thealways @(posedge clock)always block, we see thatif (~clear)it is very similar to thoseout <= 0;we’ve seen in sequentialelse if (~load)circuit descriptions so far.out <= in;The register is positiveendmoduleedge triggered but doesnot have an asynchroExample 2.24 Register Modulenous reset.
To go alongwith the register modulesdefined for our datapath, it has two control points: clear and load. These controlpoints, when asserted, cause the register to perform the specified function. If inputclear is asserted, it will load 0 at the clock edge. If load is asserted, it will load input ininto register out at the clock edge. If both are asserted, then the register will performthe clear function.This example introduces a new statement, the parameter statement.
The parameterdefines a name to have a constant value; in this case Width has the value 8. This nameis known within the module and can be used in any of the statements. Here we see itbeing used to define the default value for the left-most bit number in the vector definitions of the output and register out and the input in. Given that Width is defined tobe 8, the left-most bit is numbered 7 (i.e., 8-1) and out and in both have a bitwidth ofeight (i.e., bits 7 through 0). What is interesting about a parameter is that the defaultvalue can be overridden at instantiation time; however it cannot be changed duringthe simulation.
Thus, this module definition can be used to instantiate registers ofdifferent bitwidth. We will see how shortly.The adder module is shown inExample 2.25. It is parameterized to havea default bitwidth of eight. The assignstatement in this example shows a meansof generating our “adder” function. Theoutput sum is assigned the arithmeticsum of inputs a and b using the “+” operator. The assign statement is discussed further in Chapter 6.module adder#(parameter Width = 8)(input [Width-1:0] a,b,output [Width-1:0] sum);assign sum = a + b;endmoduleExample 2.25 The Adder ModuleLogic SynthesisThe compareLT and comparemodules are shown inExample 2.26, again using thecontinuous assign statement. Inthe compareLT module, a iscompared to b.
If a is less than b,then out is set to TRUE. Otherwise it is set to FALSE. The comparemodule for comparingi with 10 in our computation issimilar to this module exceptwith the “<=” operator instead ofthe “<“ operator. The width ofthese modules are also parameterized. Don’t be confused by thesecond assign statement, namely:assign out = a <= b;61module compareLT // compares a < b#(parameter Width = 8)(input[Width-1:0] a, b,outputout);assign out = a < b;endmodulemodule compare// compares a <= b#(parameterWidth = 8)(input[Width-1:0] a, b,outputout);assign out = a <= b;endmoduleExample 2.26 The CompareLT andCompareModulesThis does not assign b to a with anon-blocking assignment, and then assign a to out with a blocking assignment.
Onlyone assignment is allowed in a statement. Thus by their position in the statement, weknow that the first is an assignment and the second is a less than or equal comparison.The adder, compareand compareLT modules could have written using thecombinational version of the always block. As used in these examples, the two formsare equivalent. Typically, the continuous assign approach is used when a combinational function can be described in a simple statement. More complex combinationalfunctions, including ones with don’t care specifications, are typically easier to describewith a combinational always statement.References: continuous assign 6.32.7.4 Wiring the Datapath TogetherNow we build a module to instantiate all of the necessary FSM and datapath modulesand wire them together. This module, shown in Example 2.27, begins by declaringthe 8-bit wires needed to connect the datapath modules together, followed by the 1bit wires to connect the control lines to the FSM.
Following the wire definitions, themodule instantiations specify the interconnection shown in Figure 2.4.Note that this module also defines a Width parameter, uses it in the wire definitions, and also in the module instantiations. Consider the module instantiation for theregister I from Example 2.27.The Verilog Hardware Description Language62module sillyComputation#(parameter Width =(inputinput [Width-1:0]output [Width-1:0]wire[Width-1:0]wire8)ck, reset,yln,y,x);i, addiOut, addxOut;yLoad, yClear, xLoad, xClear, iLoad, iClear;register#(Width)IYXadder#(Width)addI (addiOut, 'b1, i),addX (addxOut, y, x);compareLTcomparefs m(xLT0,endmodule#(Width)#(Width)(i, addiOut, iClear, iLoad, ck),(y, yIn, yClear, yLoad, ck),(x, addxOut, xClear, xLoad, ck);cmpX (x, 'b0, xLT0);cmpI (i, 'd10,);ctlyLoad, yClear, xLoad, xClear, iLoad, iClear, ck, reset);Example 2.27 Combining the FSM and Datapathregister#(Width)I(i, addiOut, iClear, iLoad, ck),What is new here is the second item on the line, “#( Width)”.
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