Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 14
Текст из файла (страница 14)
In the above example, q is loaded with input d.Thus, “clock” is not a reserved word. Rather, the synthesis tools infer the specialclock input from assignment’s position in the control path; it is the action thatoccurs when none of the set or reset actions occur.All procedural assignments in an always block must either be blocking or nonblocking assignments. They cannot be mixed within an always block.
Non-blocking assignments (“<=”) are the assignment operator of choice when specifying theedge-sensitive behavior of a circuit. The “<=” states that all the transfers in thewhole system that are specified to occur on the edge in the sensitivity list shouldThe Verilog Hardware Description Language52occur concurrently.
Although descriptions using the regular “=” will synthesizeproperly, they may not simulate properly. Since both simulation and synthesis aregenerally of importance, use “<=” for edge sensitive circuits.The sensitivity list of the always block includes only the edges for the clock, resetand preset conditions.These are the only inputs that can cause a state change. For instance, if we aredescribing a D flip flop, a change on D will not change the flip flop state.
So the Dinput is not included in the sensitivity list.Any register assigned to in the sequential always block will be implemented usingflip flops in the resulting synthesized circuit. Thus you cannot describe purelycombinational logic in the same always block where you describe sequential logic.You can write a combinational expression, but the result of that expression will beevaluated at a clock edge and loaded into a register.References: non-blocking versus blocking assignment 8.4.2.4.3 SummaryLatches and flip flops are fundamental components of register-transfer level systems.Their complex behavior requires that a strict format be used in their specification.
Wehave only covered the basics of their specification. Most synthesis tools provide compiler directives to aid in making sure the proper library element is selected to implement the specified behavior. Read the synthesis tool manual closely.2.5 Inferring Tri-State DevicesTri-state devices are combinational logiccircuits that have three output values:one, zero, and high impedance (z). Having special, non-typical capabilities,these devices must be inferred from thedescription. Example 2.20 illustrates atri-state inference.module synTriState(output reg bus,inputin, driveEnable);always @(*)if (driveEnable)bus = in;else bus = 1'bz;endmoduleThe always statement in this modulefollows the form for describing a combinational logic function.
The special situExample 2.20 Inferring a Tri-Stateation here is that a condition (in thisDevicecase, driveEnable) specifies a case wherethe output will be high impedance. Synthesis tools infer that this condition will be thetri-state enable in the final implementation.Logic Synthesis532.6 Describing Finite State MachinesWe have seen how to specify combinational logic and sequential elements to a synthesis tool. In this section we will combine these into the specification of a finite statemachine. The standard form of a finite state machine is shown in Figure 2.1.
Themachine has inputs outputs and flip flops holding the current state. The outputs can either be a function solely of the current state, in which case this is a Mooremachine. Or, they can be a function of the current state and input, in which case thisis a Mealy machine.
The input to the flip flops is the next state; this is a combinationalfunction of the current state and inputs.The Verilog description of a finite state machine (FSM) follows this model closely.The outer box of Figure 2.1 will be the FSM module. The two inner boxes will be twoseparate always statements. One will describe the combinational logic functions of thenext state and output. The other will describe the state register.2.6.1 An Example of a Finite State MachineAn example of an FSM description will be presented using the explicit style of FSMdescription.
In this style, a case statement is used to specify the actions in each of themachine’s states and the transitions between states. Consider the state transition diagram shown in Figure 2.2. Six states and their state transitions are shown with oneinput and three output bits specified. Example 2.21 is the Verilog description of thisFSM.The first always statement is a description of the combinational output (out) andnext state (nextState) functions. The input set for these functions contains the input iand the register currentState.
Any change on either of these will cause the alwaysstatement to be re-evaluated. The single statement within the always is a case state-54The Verilog Hardware Description Languagement indicating the actions to be performed in each state. The controlling expressionfor the case is the state variable (currentState). Thus, depending on what state themachine is in, only the specified actions occur. Note that in each case item, the twocombinational functions being computed (out and nextState) are assigned to. In addition, a default case item is listed representing the remaining unassigned states. Thedefault sends the machine to state A which is equivalent to a reset. By arbitrarychoice, out is set to don’t care in the unassigned states.This always statement will result in combinational logic because: the sensitivity listcontains all of the input set, there are no edge specifiers in the sensitivity list, and forevery control path, both of the combinational outputs have been assigned to.
Thisincludes every possible case item. Thus, there will be no inferred latches. Note that adefault case item was used here instead of specifying that this is a full case. This allowsus to specify the reset state as the next state in case there is an error in operation — forinstance, the logic circuit somehow gets into an undefined state. Although we specified that the output in this situation is a don’t care, we could have made a specificationhere too.The second always statement infers the state register with its reset condition.
Inthis case, reset is asserted low and will cause the machine to go into state A. If reset isnot asserted, then the normal action of the always will be to load currentState withthe value of nextState, changing the state of the FSM on the positive edge of clock.Notice that currentState is assigned to in every control path of the always — sowhy is a flip flop inferred? The reason is that the edge specifications in the eventexpression cause any register assigned to in the block to be implemented using flipflops.
You cannot specify combinational logic in an always block with edge triggers inthe sensitivity list. This is why we need two always blocks to specify an FSM: one forthe state register, and the other for the combinational logic.The localparam statement specifies the state assignment for the system. Since theseare treated as constants, they cannot be directly overridden by instantiation.Together, these two always statements work together to implement the functionality of a finite state machine. The output of the second always is the current state of theLogic Synthesis55module fsm(inputi, clock, reset,output reg [2:0] out);reg[2:0]currentState, nextState;localparam [2:0] A = 3'b000,// The state labels and their assignmentsB = 3'b001,C = 3'b010,D = 3'b011,E = 3'b100,F = 3'b101;always @(*)// The combinational logiccase (currentState)A: beginnextState = (i == 0) ? A : B;out = (i == 0) ? 3'b000 : 3'b100;endB: beginnextState = (i == 0) ? A : C;out = (i == 0) ? 3'b000 : 3'b100;endC: beginnextState = (i == 0) ? A : D;out = (i == 0) ? 3'b000 : 3'b101;endD: beginnextState = (i == 0) ? D : E;out = (i== 0) ? 3'b010 : 3'b110;endE: beginnextState = (i == 0) ? D : F;out = (i == 0) ? 3'b010 : 3'b110;endF: beginnextState = D;out = (i == 0) ? 3'b000 : 3'b101;enddefault: begin // oops, undefined states.
Go to state AnextState = A;out = (i == 0) ? 3'bxxx : 3'bxxx;endendcaseThe Verilog Hardware Description Language56always @(posedge clock or negedge reset) //The state registerif (~reset)currentState <= A;// the reset stateelsecurrentState <= nextState;endmoduleExample 2.21 A Simple Finite State MachineFSM and it is in the input set of the first always statement. The first always statementis a description of combinational logic that produces the output and the next statefunctions.References: parameters 5.2; non-blocking assignment 8.4; implicit style 2.6.2.2.6.2 An Alternate Approach to FSM SpecificationThe above explicit approach for specifying FSMs is quite general, allowing for arbitrary state machines to be specified.
If an FSM is a single loop without any conditional next states, an implicit style of specification may be used.The basic form of an implicitFSM specification is illustrated inExample 2.22. The single alwaysstatement lists several clock events,all based on the same edge (positiveor negative). Since the always specifies a sequential loop, each state isexecuted in order and the loop executes continuously.
Thus, there is nonext state function to be specified.In this particular example, a flowof data is described. Each state computes an output (temp and dataOut)that is used in later states. The outputof the final state (dataOut) is theoutput of the FSM. Thus, a newresult is produced every third clockperiod in dataOut.module synImplicit(input[7:0] dataIn, c1, c2,inputclock,output reg [7:0] dataOut);reg[7:0]temp;always begin@ (posedge clock)temp = dataIn + c1;@ (posedge clock)temp = temp & c2;@ (posedge clock)dataOut = temp - c1;endendmoduleExample 2.22 An Implicit FSMLogic SynthesisAnother example of a flow ofdata is a pipeline, illustrated inExample 2.23 using a slightlydifferent calculation. Here aresult is produced every clockperiod in dataOut.
In this case,three FSMs are specified; one foreach stage of the pipe. At everyclock event, each stage computesa new output (stageOne, stageTwo, and dataOut). Since thesevariables are used on the lefthand side of a procedural statement in an always block with anedge specifier, there are implemented with registers. The nonblocking assignment (<=) mustbe used here so that the simulation results will be correct.Figure 2.3 shows a simplifiedform of the implementation ofmodule synPipe.References: explicit style 2.6.157module synPipe(input[7:0] dataIn, c1, c2,inputclock,output reg [7:0] dataOut);regreg[7:0][7:0]stageOne;stageTwo;always @ (posedge clock)stageOne <= dataIn + c1;always @ (posedge clock)stageTwo <= stageOne & c2;always @ (posedge clock)dataOut <= stageTwo + stageOne;endmoduleExample 2.23 A PipelineThe Verilog Hardware Description Language582.7 Finite State Machine and DatapathWe’ve used the language to specify combinational logic and finite state machines.Now we’ll move up to specifying register transfer level systems.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
