Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 29
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There is a procedural version of the continuous assignmentstatement that allows for continuous assignments to be made to registers for certainspecified periods of time. Since the assignment is not in force forever, as is true withthe continuous assignment, we call this the procedural continuous assignment (thesewere called “quasi-continuous” in earlier versions of the manuals), While the procedural continuous assignment is in effect, the statement acts like a continuous assign.Concurrent Processes137Consider the example of a presetmodule dFlopand clear on a register shown in(inputpreset, clear,Example 4.12.
Note first that theoutput reg q,difference between continuous andinputclock, d);procedural continuous is immediately obvious from the context; thealwaysprocedural continuous assignment@(clear, preset)is a procedural statement executedbeginonly when control passes to it. (Theif(!clear)continuous assignment is always#10 assign q = 0;active, changing its outputs whenelse if (!preset)ever its inputs change.) In this#10 assign q = 1;example, the first always statementelsedescribes a process that reacts to a#10 deassign q;change in either the clear or presetendsignals. If clear becomes zero, thenwe assign register q to be zero. Ifalwayspreset becomes zero, then we assign@(negedge clock)register q to be one. When a changeq = #10 d;occurs and neither are zero, then weendmoduledeassign q (essentially undoing theprevious procedural continuous Example 4.12 Flip Flop With ProceduralContinuous Assignmentassignment), and then q can beloaded with a value using the normal clock method described by the second always statement.The general form of the assignment is:statementprocedural_continuous_assignmentsprocedural_continuous_assigmnentassign variable_assignment;deassign variable_lvalue;variable_assignmentvariable_lvalue = expressionIt is important to note that the procedural continuous assignment overrides a normal procedural assignment to a register.
While the procedural continuous assignmentis in effect, the reg_assignment acts like a continuous assignment. Thus, even if thenegative edge of the clock occurred as watched for in the second always statement, theprocedural assignment of d to q would not take effect. Further, if the value of theright-hand side of a procedural continuous assignment changes (it was not a constant138The Verilog Hardware Description Languageas in the above example), then the left-hand side will follow it.
The value proceduralcontinuously assigned remains in the register after the deassignment.References: continuous assignment 6.3; procedural assignment 3.1; event control with or 4.2.14.9 Sequential and Parallel BlocksThe begin-end blocks that we have seen so far are examples of sequential blocks.Although their main use is to group multiple procedural statements into one compound statement, they also allow for the new definition of parameters, registers, andevent declarations when the begin-end blocks are named. Thus new local variablesmay be specified and accessed within a named begin-end block.An alternate version module microprocessor;of the sequential beginalwaysend block is the parallelbeginor fork-join block shownresetSequence;below.
Each statement infork: mainWorkthe fork-join block is aforeverseparate process thatfetchAndExecuteInstructions;begins when control is@(posedge reset)passed to the fork. Thedisable mainWork;join waits for all of thejoinprocesses to completeendbefore continuing with endmodulethenextstatementbeyond the fork-join Example 4.13 An Illustration of the Fork-Join Blockblock.This example illustrates the description of an asynchronous reset restarting a process.
A resetSequence initializes registers and then begins the fork-join block namedmainWork. The first statement of the fork is a forever loop that describes the mainbehavior of the microprocessor. The second statement is the process that watches forthe positive edge of the reset signal. When the positive edge of the reset occurs, themainWork block is disabled.
As described previously, when a block is disabled, everything in the named block is disabled and execution continues with the next statement,in this case the next iteration of the always statement. Thus, no matter what was happening in the fetch and execute behavior of the system, the reset is able to asynchronously restart the whole system.The general form for the parallel block is given below.
Like the named (sequential)blocks previously described, naming the block allows for the optionalblock_declarations that can introduce new names for the scope of the block.Concurrent Processes139statementpar_blockpar_blockfork [: block _identifier { block_item_declaration } ]{ statement}joinblock_item_declarationparameter_declarationlocal_parameter_declarationinteger_declarationreal_declarationtime_declarationrealtime_declarationevent_declarationExample 4.14 shows a less abstractuseof thefork-joinblock.Example 4.11 has been rewritten, thistime with a single always that includesa fork-join.module simpleTutorialWithReset(inputclock, reset,output reg [7:0] y, x_;Again, it is important to note thatwe consider each of the statements ofthe fork-join as a separate process.This example essentially replaced twoalways statements by one that has afork-join.ComparingbacktoExample 4.11 serves to enforce furtherthe notion that each statement in thefork-join should be considered, at leastconceptually, a separate process.always fork: main@(negedge reset)disable main;beginwait (reset);@(posedge clock) x <= 0;i = 0;while (i <= 10) begin@(posedge clock);x <= x + y;i = i + 1;end@(posedge clock);if (x < 0)y<=0;else x <= 0;endjoinendmoduleReferences: named blocks 4.6reg[7:0]i;Example 4.14 Fork-Join Version of SimpleTutorial ExampleThe Verilog Hardware Description Language1404.10 Exercises4.1Will the following two fragments of Verilog code result in the same behavior?Why or why not?@(posedge exp)#1 statement1;4.2wait (exp)#1 statement 1;Rewrite the consumer and producer modules in Examples 4.6 at the behaviorallevel, such that a common clock signal controls the timing of the data transferbetween the modules.
On consecutive positive clock edges, the following is tohappen: 1) the producer sets up the data on its output, 2) the consumer reads thedata, 3) the producer sets up its next data value, and so on.For the design to be valid there needs to be a suitable power-on initializationmechanism. Find a solution to this and include it in the model.4.3 Extend Examples 4.6 to include internal processing between the consumer andproducer parts that is a simple increment operation with a delay of 10 timeunits.
Connect an instance of this module in a loop such that data can flowaround the loop forever with data being incremented each time around. Addextra code to initialize the model for execution (See figure, top of next page).4.4 Consider four named events: e1, e2, e3, and e. Write a description to triggerevent e after e1, e2, and e3 have occurred in a strict sequence Namely, if anyevent goes out of order the sequence is to be reset. Then, write a description totrigger event e after e1, e2, and e3 have each occurred three times in any order.4.5The following combinational logic block has three inputs and an output. Thecircuit was built in some screwy technology and then analyzed.
We now want toinsert the correct input-to-output timing information into the circuit (internalnode timings need not be correct).Concurrent Processes141Here are the circuit timings that must be represented in the circuit.The delay of a rising or falling edge on a or b to output f: 15 time unitsThe delay of a rising or falling edge on c to output f: 10 time unitsYes, those times are rather strange given the logic diagram.
However, this is ascrewy technology and the transistor implementation made for some strange,but actual, time delays.Assume a, b, and c are outputs of synchronously clocked flip flops. Write thebehavioral Verilog description that will be correct in functionality and timing.4.6 For the pipeline processor in Example 4.10, add part of the instruction decodelogic (i.e., like the case statement in the execute stage) into the fetch stage.
Useit instead of the skip variable to determine how to load the pc.4.7 For the mark1PipeStage module in Example 4.10, write an initial statementthat will load the processor’s memory and execute several instructions. Add amonitor statement and other initializations and clocking as needed. Write aprogram with the given machine instructions that will execute the followingpseudo code:142The Verilog Hardware Description Languageif ((m[4] - m[5]) < 0)m[4] = 17;elsem[4] = -10;4.8 Add a third stage to the pipeline of Example 4.10. The second stage should onlyfetch operands; values read from memory should be put in a memory data register (mdr).
The third stage will execute the instructions, loading the resulting values (mdr) in acc, pctemp, or m. Assume that the memory has multiple read andwrite ports. Handle any interstage conflicts that may arise.5Module HierarchyA structural model of a digital system uses Verilog module definitions to describearbitrarily complex elements composed of other modules and gate primitives. As wehave seen in earlier examples, a structural module may contain a combination ofbehavioral modeling statements (an always statement), continuous assignment statements (an assign statement), or module instantiations referencing other modules orgate level primitives.
By using module definitions to describe complex modules, thedesigner can better manage the complexity of a design. In this chapter we exploremodule hierarchy and how it is specified as we cover instantiation, parameterizedmodules, and iterative generation.5.1 Module Instantiation and Port SpecificationsA port of a module can be viewed as providing a link or connection between twoitems, one internal to the module instance and one external to it. We have seennumerous examples of the specification of module ports.An input port specifies the internal name for a vector or scalar that is driven by anexternal entity.
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