Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 43

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Thus, instead@ (posedge phi2)of the statement “qInternal = d” being exe#2 q = qInternal;cuted right after a positive edge is seen onendphi1, an evaluation event for the process isendmodulescheduled two time units later. At thatpoint, the process resumes executing by Example 8.5 Delay in a BehavioralModelassigning to qInternal.Registers are assigned new values as a result of executing behavioral models. Thevalues are assigned immediately without need for creating update events. Thus if aregister is assigned to on the left-hand side of a procedural expression, and immediately used in the next statement on the right-hand side, its new value is used. In addition, registers that are outputs of the process will also create update events.

So, if aregister is used as a source in a continuous assignment, or in a wire, or if anotherbehavioral process is waiting (with @ or wait) for a change in the register, the updateevent will cause evaluation events to be scheduled.Behavioral models, exhibiting the procedural timing model, can be simulated usingthe algorithm of Figure 8.3 if we allow for fanout lists to be changed during executionof the models, and if register values are updated so they are available for the nextbehavioral statements.8.3 Non-Deterministic Behavior of theSimulation AlgorithmVerilog is a concurrent language, allowing for the specification of actions that occur atthe same time. Executing these actions requires their serialization because the computer being used is not as parallel as the hardware being modeled.

There are twosources of non-deterministic behavior in the Verilog language: arbitrary executionorder in zero time, and arbitrary interleaving of statements from other processes;these will be discussed in this section. Although one simulator will always produce theAdvanced Timing221same results given the same simulation model and inputs, a different simulator versionor a different supplier’s simulator may choose to execute these same events in a different order. Thus, we say that the results are not deterministic.8.3.1 Near a Black HoleA simulator executes events scheduled for the same time in a group. It may take several simulation cycles to execute all of these events because some events may createother events for the current time. We speak of executing events for the same time asexecuting them in zero-time.

It is not that these take no time to execute. Rather all ofthe events occur without the passage of simulation time. They occur in zero-time.The “For each” statement in the scheduling algorithm of Figure 8.3 removes oneor more events from the event list for execution during the current simulation time.Further, it specifies that the order in whichthese events are executed is arbitrary.

Thearbitrary execution order of events in zerotime is a source of non-determinism in thesimulation language. When writing models, one needs to be sensitive to the factthat the ordering of events in zero-time isunspecified.module stupidVerilogTricks(output reg f,inputa, b);regq;initialf=0;always@ (posedge a)# 10 q = b;A contrived illustration of non-deternot(qBar, q);minism is shown in Example 8.6. Theexample has three behavioral processesalways(one initial and two always statements),@qand one gate model.

Assume at some timef = qBar;q = 0, f = qBar = b = 1, and a = 0. Later, aendmodulechanges to 1. a changing to one will createa positive edge that will cause the first Example 8.6 Problems in Zero-Timealways statement to begin executing. Thealways statement will delay ten time units, set q equal to b (which is 1), and then waitfor the next positive edge on a. Setting q to a new value will cause evaluation eventsfor the two elements that are on q’s fanout — the second always statement and the notgate. In the next simulation cycle, these will be removed from the event list and executed in arbitrary order.

Note however that depending on the order, a different valuefor output f will be obtained. If the always statement is executed first, f will remain 1.If the not gate is executed first, f will be set to 0.222The Verilog Hardware Description LanguageWhich answer is correct? Based on thealwayssemantics of the language, either one is correct.beginThey are both correct because the simulator is@qallowed to take events out of the event list forqBar = ~q;the current time and execute them in whateverf = qBar;order it pleases. If you think that q and qBarend(and thus f) should always appear to have complementary values, then you need to change the Example 8.7 One Correction toExample 8.6simulation model. For example, one change isto combine the second always statement andthe not gate instantiation, leaving only the always statement shown in Example 8.7.This solution will maintain the timing.

Also, placing a “#1” before “f = qBar” inExample 8.6 will ensure the “correct” value is loaded into f — however, the timingcharacteristics of the module would be changed too. A solution that maintains thetiming uses “#0” instead of the “#1” in the “f = qBar” statement. This solution will bediscussed further in section 8.4.Although the above example was conmodule goesBothWaystrived, be assured that non-determinism sur(output [2:1]faces in uncontrived examples.

Consider theinputclock);ripple counter in Example 8.8. Here two Dflip flops are connected together in a counterwire q1, q2;configuration; the low order flip flop (instanceassigna) is connected in a toggle mode. The higherorder bit (b) has the low order bit as its input.dffa (ql, ~ql, clock),We would expect the counter to incrementb (q2, ql, clock);through the states 00, 01, 10, 11, 00, … at theendmodulepositive edge of the clock.

However, on closerinspection we see that the “q = d” statementmodule dffof both instances of the dff is scheduled to(output reg q,continue executing three time units into theinputd, clock);future. At that time, the scheduler will takeboth of these evaluation events off of thealwaysevent list and execute them in arbitrary order.@(posedge clock)Of course, the order does matter. Executing#3 q = d;instance a first will lead to an incorrect countendmoduleing sequence (00, 11, 00, ...). Executinginstance b first will produce intended order.

Example 8.8 Non-Determinism in aFlip Flop ModelThis problem can be corrected by using the intra-assignment delay statement“q = #3 d;” in the dff module. This statement will cause all of the d inputs of the dffinstances to be sampled and stored as update events in the event list before any of theupdates are made to the instances of q. Thus, the instances can be executed in anyorder and the behavior is deterministic. The problem can also be corrected by usingnon-blocking assignment: “q <= d;” in the dff module.

Here the non-blocking assign-Advanced Timing223ment works with the clock edge to separate the reading of all of the d’s from theupdating of the q’s.The fact that events in zero-time can be executed in arbitrary order is part of thebasic definition of the language. Non-deterministic behavior in a design reflects eitherpoor usage of the modeling constructs, or a real race condition. Non-determinism isallowed in the language both for efficiency reasons and because it happens in real life… “non-determinism happens”. Care must be exercised when writing models withoutraces so that the results will be deterministic given any ordering of execution in zerotime.8.3.2 It’s a Concurrent LanguageThe second source of non-determinism in Verilog stems from potential interleavingof the statements in different behavioral processes.

By behavioral process models, wemean the behavioral statements found in always and initial statements. Update eventsand all evaluation events except for the execution of behavioral process models areatomic actions; these events are guaranteed to be executed in their entirety beforeanother event is executed. The behavioral process models found in initial and alwaysstatements live by a different set of rules.Consider first a software programming environment.

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