Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 45
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The nonblocking assignment serves to separate the values existing before the clock edge fromthose generated by the clock edge. Here, the values on the right-hand side of the nonblocking assignment are values before the clock edge; those on the left-hand side aregenerated by the clock edge.Using non-blocking assignments causes these two assignments to be concurrent —to appear to happen at the same time. The first statement in the always block is executed and a non-blocking update for cS1 is scheduled for the current time. However,the update is not made immediately and execution continues with the second line.228The Verilog Hardware Description LanguageHere a non-blocking update for cS0 is scheduled for the current time.
This update isnot made immediately and execution continues with the always block waiting for thenext posedge clock. Thus, the cS1 calculated on the first line is not the same valueused on the right-hand side of next statement.When will the values of cS1 and cS0be updated? They will be updated onlyafter all blocking updates for the currenttime are executed. This includes anyblocking updates or evaluation eventsgenerated from them. Thus all righthand sides will be evaluated before anyof the left-hand sides are updated.
Theeffect is that all non-blocking assignments appear to happen concurrentlyacross the whole design. The order ofthe two statements for cS1 and cS0could be switched in the descriptionwith no change in the resulting value.module fsm(output reginputcS1, cS0,in, clock);always @(posedge clock) begincS1<= in & cS0;cS0 <= in | cS1;endendmoduleExample 8.10 Illustrating the NonBlocking AssignmentThe powerful feature of the non-blocking assignment is that not only are the twostatements in this module concurrent, but all non-blocking assignments waiting onthe same edge in any of the always or initial statements in the whole design are concurrent.8.4.3 Extending the Event-Driven Scheduling AlgorithmAn expanded version of the simulator scheduler algorithm (previously shown inFigure 8.3) is shown in Figure 8.6. Several elements have changed.
First, the termregular event has been used to include all events other than the non-blocking updateevents. Thus regular events include blocking assignment updates and evaluationevents for behavioral processes and gate models. Secondly, the then clause of the second if has been changed to look for non-blocking update events when all regularevents have been executed. Conceptually, the non-blocking update events are changedto regular events so that the rest of the scheduler algorithm can handle them directly.Finally, monitor events are handled after all of the above events have been executed.The event list can be thought of as having separate horizontal layers as shown inFigure 8.7.
For any given time in the event list, there are three separate layers: theregular events, the non-blocking events, and the monitor events. The scheduler algorithm removes the regular events from the list and executes them, possibly causingother events to be scheduled in this and other time slots. Regular events for time areput in the list in the regular event section; these will be removed during the next simulation cycle.
Other events will be scheduled into their respective sections or intoevent lists for future times.Advanced Timing229When we get to the next simulation cycle and there are more regular events, theseare handled as just described. When there are no more regular events for the currenttime, events from the non-blocking layer are moved to the regular event layer andexecuted.
These in turn may cause other regular events and non-blocking eventswhich are scheduled into their respective sections. The event scheduling algorithmcontinues repeatedly executing all of the regular events for the current time, followedby the non-blocking events for the current time until no more events (regular or nonblocking) exist for the current time. At this point, the scheduler handles monitorevents. These are inserted in the monitor events layer when the input to a monitorstatement changes.
These are the last to be handled before time is advanced. Theycause no further events.Given this background, here is a list of how the different procedural assignmentsare handled by the simulation scheduler:The Verilog Hardware Description Language230“a = b;”“a <= b;”b is calculated and used immediately to update a. Note that the nextstatement in the behavioral process that uses a as a source will usethis new value. If a is an output of the process, elements on a’sfanout list are scheduled in the current time as a regular evaluationevents.b is calculated and a non-blocking update event is scheduled for aduring the current time.
Execution of the process continues. Thisnew value for a will not be seen by other elements (not even the currently executing behavioral process) until the non-blocking updateevents are executed.“a = #0 b;”b is calculated and an update event for a is scheduled as a regularevent in the current time.
The current process will be blocked untilthe next simulation cycle when the update of a will occur and theprocess will continue executing.“a <= #0 b;”b is calculated and a non-blocking update event is scheduled for thecurrent time. The current process will continue executing. Theupdate event will be executed after all regular events for the currenttime are executed. The same as “a <= b;”.“a= #4 b;”This is like “a = #0 b;” except that the update event and the continuation of the process is scheduled 4 time units into the future.“a <= #4 b;”This is like “a <= #0 b;” except that a will not be updated (using anon-blocking update event) until 4 time units into the future.“#3 a = b;”Wait 3 time units before doing the action for “a = b;” specifiedabove.
The value assigned to a will be the value of b 3 time unitshence.Advanced Timing231“#3 a <= b;” Wait 3 time units before doing the action for “a <= b;” specifiedabove. The value assigned to a will be the value of b 3 time unitshence.Note that in the above situations the value assigned to a is the same. (Well okay, thevalue of b in the last two examples could change in the next three time units. But forthose two cases, the value assigned to a would be the same.) The differences lie inwhat part of the event list the update is scheduled in, whether the value is available inthe next behavioral statement, and whether the current process is blocked because ofthe #.8.4.4 Illustrating Non-Blocking AssignmentsAs presented in the previous section, the non-blocking assignment allows us to schedule events to occur at the end of a time step, either the current one or a future one.Further, they allow the process to continue executing.
As with blocking assignments,event control and repeat constructs can be specified within the assignment statement.The general form for the non-blocking assignment is shown below:nonblocking_assignmentvaiable_lvalue <= [ delay_or_event_control ] expressiondelay_or_event_controldelay_control|event_control| repeat ( expression ) event_controldelay _control# delay_value| # (mintypmax_expression)event_control@ event_identifier|@ (event expression)|@*|@(*)event_expressionexpressionhierarchical_identifierposedge_expreessionnegedge_expressionevent_expression or event_expressionevent_expression , event_expression232The Verilog Hardware Description LanguageWe have already illustrated the optional delay control.
This section will discuss theevent control and repeat constructs.A differentiating feature of the nonmodule inertialNandblocking assignment is the fact that it#(parameter pDelay = 5)schedules an assignment but does not(output reg f,block the current process from executinginputa, b);further. Consider the behavioral model ofa NAND gate, shown in Example 8.11,alwaysthat changes the inertial delay of a gate to@(a,b)zero. Any change on a or b will cause anf <= #pDelay~(a & b);update event for f to be scheduled pDelay endmoduletime units in the future. A non-blockingassignment is necessary here because it Example 8.11 Illustration of NonBlocking Assignmentallows the behavioral model to remainsensitive to its inputs; a change one timeunit later will cause another update event on f. If a blocking assignment had beenused, the behavioral model would be delaying and the input change one time unitlater would have been missed until after the delay.Figure 8.8 shows the output waveforms for the NAND gate of Example 8.11 (iDelay= 0) as compared to an instantiated NAND gate.
The instantiated NAND gate’s outputonly responds to a set of inputs when they have been supporting the new output forthe propagation time. Thus the output does not see the pulses on the inputs and twicean output update event is cancelled (see “*”). With the inertial delay equal to 0, theinput pulses show up a propagation time (pDelay) later. Note at the right that aninput “pulse” can be generated from two different inputs changing. Because of the 0inertial delay, this pulse is seen on the output at the right of the figure.Advanced Timing233Consider a behavioral model of a pipelined multiplier shown in Example 8.12. Thelatency for the multiplier is four clock periods and it can accept a new set of inputseach clock period.
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